PM6641 데이터 시트보기 (PDF) - STMicroelectronics

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PM6641

Monolithic VR for chipset and DDR2/3 supply for ultra-mobile PC (UMPC) applications

STMicroelectronics 

PM6641

Pin settings

Table 2. Pin functions (continued)

n°

Pin

Function

26

SS_1S5

Positive terminal of the external soft-start capacitor for 1.5 V rail.

See Chapter 7.6: Outputs soft-start on page 28 section for details.

Loop compensation output for 1.5 V rail. Chapter 7.3: SW regulators control

27 COMP_1S5 loop on page 24 and Chapter 8.4: SW regulator compensation components

selection on page 38 sections for details.

28

VFB_1S5

Feedback input for 1.5 V rail.

See Chapter 7.5: Output voltage divider on page 27 section for details

29 SGND_1S5 Switcher power ground for 1.5 V rail.

30 SGND_1S5 Switcher power ground for 1.5 V rail.

31 VSW_1S5 Switch node for 1.5 V rail.

32 VSW_1S5 Switch node for 1.5 V rail.

33

VIN_1S5 Power supply input for 1.5 V rail.

34

EN_1S05 Enable input for 1.05 V rail.

35

EN_1S5 Enable input for 1.5 V rail.

36

EN_VTT

Enable input for VTT rail. High in S0 system states. See Chapter 7.1.4: S3

and S5 power management pins on page 22 section for details.

Enable input for 1.8 V (VDDQ) rail. High in S0-S3 system states.

37

EN_1S8 See Chapter 7.1.4: S3 and S5 power management pins on page 22 section

for details.

38

AGND

Analog and signal ground.

39

SET_PH1

Switching regulator phase control.

See Chapter 7.9: Phase management on page 30 section for details.

40

AGND

Analog and signal ground.

41

AVCC

Analog circuitry supply. Connect to +5 V by a simple RC filter.

42

VTTGND LDO linear regulator power ground.

LDO linear regulator output. DDR2-3 termination voltage. See Chapter 7.1:

43

VTT

Memory supply on page 20 and Chapter 7.1.2: VTT LDO and VTTREF

buffered reference on page 21 sections for details.

44

LDOIN LDO linear regulator input. Typically connected to the 1.8 V rail.

Reference voltage buffer output. See Chapter 7.1: Memory supply on

45

VTTREF page 20 and Chapter 7.1.2: VTT LDO and VTTREF buffered reference on

page 21 sections for details.

46

DSCG

Tracking/non-tracking discharge selection for DDR2-3 section. See

Chapter 7.7: Outputs soft-end on page 29 section for details.

47

VTTFB Feedback input for VTT linear regulator output.

48

VCC

+5 V switching circuitry supply. Bypass to AGND by a 100 nF capacitor.

Doc ID 13510 Rev 3

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