PM6670ASTR 데이터 시트보기 (PDF) - STMicroelectronics

부품명

상세내역

제조사

PM6670ASTR

Complete DDR2/3 memory power supply controller

STMicroelectronics 

PM6670AS

Electrical characteristics

Table 6.

Symbol

Electrical characteristics (continued)

Parameter

Test condition

Min Typ Max Unit

VTTREF discharge

resistance in non-tracking

discharge mode

VDDQ Output threshold

synchronous for final tracking

to non-tracking discharge

transition

1

1.5

2

kΩ

0.2

0.4

0.6

V

VTT LDO section

ILDOIN,ON

LDO input bias current in full-

on state

S3 = S5 = +5 V,

No Load on VTT

1

10

ILDOIN, LDO input bias current in

STR suspend-to-RAM state

S3 = 0 V, S5 = +5 V,

No Load on VTT

10

μA

ILDOIN, LDO input bias current in

STD suspend-to-disk state

S3 = S5 = 0 V, No Load on VTT

1

IVTTSNS, VTTSNS bias current

S3 = +5 V, S5 = +5 V,

1

BIAS

VVTTSNS = VVSNS /2

IVTTSNS, VTTSNS leakage current

LEAK

S3 = 0V, S5 = +5 V,

VVTTSNS = VVSNS /2

1

μA

IVTT,LEAK VTT leakage current

S3 = 0V, S5 = +5 V,

VVTT = VVSNS /2

-10

10

LDO linear regulator output S3 = S5= +5 V, IVTT = 0 A, MODE =

voltage (DDR2)

DDRSEL = +5 V

0.9

LDO linear regulator output

voltage (DDR3)

S3 = S5= +5 V, IVTT = 0 A,

MODE = +5 V, DDRSEL = 0 V

V

0.75

VVTT

IVTT,CL

S3 = S5 = MODE = + 5 V,

-1 mA < IVTT < 1 mA

LDO output accuracy respect S3 = S5 = MODE = +5 V,

to VTTREF

-1 A < IVTT < 1 A

S3 = S5 = MODE = +5 V,

-2 A < IVTT < 2 A

LDO source current limit

VVTT < 1.10*(VVSNS /2)

VVTT > 1.10*(VVSNS /2)

LDO sink current limit

VVTT > 0.90*(VVSNS /2)

VVTT < 0.90*(VVSNS /2)

-20

20

-25

25

mV

-35

35

2

2.3

3

1

1.15 1.4

A

-3

-2.3

-2

-1.4 -1.15 -1

VTTREF section

VTTREF output voltage

IVTTREF = 0 A, VVSNS = 1.8 V

0.9

V

VVTTREF VTTREF output voltage

-15 mA < IVTTREF < 15 mA, VVSNS =

accuracy respect to VSNS/2 1.8 V

-2

2

%

IVTTREF VTTREF current limit

VTTREF = 0 or VSNS

±40

mA

Doc ID 14436 Rev 2

11/53

Share Link: