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M28F008 데이터 시트보기 (PDF) - Intel

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M28F008 Datasheet PDF : 28 Pages
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M28F008
Figure 1 Block Diagram
271232 – 1
Symbol
A0 – A19
DQ0 – DQ7
CE
RP
OE
WE
Type
INPUT
INPUT OUTPUT
INPUT
INPUT
INPUT
INPUT
Table 1 Pin Description
Name and Function
ADDRESS INPUTS for memory addresses Addresses are internally
latched during a write cycle
DATA INPUT OUTPUTS Inputs data and commands during Command
User Interface write cycles outputs data during memory array Status
Register and Identifier read cycles The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled Data is internally latched during a write cycle
CHIP ENABLE Activates the device’s control logic input buffers
decoders and sense amplifiers CE is active low CE high deselects the
memory device and reduces power consumption to standby levels
RESET DEEP POWERDOWN Puts the device in deep powerdown
mode RP is active low RP high gates normal operation RP also locks
out block erase or byte write operations when active low providing data
protection during power transitions RP active resets internal
automation Exit from Deep Powerdown sets device to read-array mode
OUTPUT ENABLE Gates the device’s outputs through the data buffers
during a read cycle OE is active low
WRITE ENABLE Controls writes to the Command User Interface and
array blocks WE is active low Addresses and data are latched on the
rising edge of the WE pulse
3
3

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