M28F008 데이터 시트보기 (PDF) - Intel

부품명

상세내역

제조사

M28F008

8-Mbit (1Mbit x 8) flash memory

Intel 

Table 4 Status Register Definitions

M28F008

WSMS ESS

ES

BWS VPPS

R

R

R

7

6

5

4

SR 7 e WRITE STATE MACHINE STATUS

1 e Ready

0 e Busy

SR 6 e ERASE SUSPEND STATUS

1 e Erase Suspended

0 e Erase in Progress Completed

SR 5 e ERASE STATUS

1 e Error in Block Erasure

0 e Successful Block Erase

SR 4 e BYTE WRITE STATUS

1 e Error in Byte Write

0 e Successful Byte Write

SR 3 e VPP STATUS

1 e VPP Low Detect Operation Abort

0 e VPP OK

SR 2–SR 0 e RESERVED FOR FUTURE

ENHANCEMENTS

These bits are reserved for future use and

should be masked out when polling the Status

Register

3

2

1

0

NOTES

RY BY or the Write State Machine Status bit must first

be checked to determine byte write or block erase com-

pletion before the Byte Write or Erase Status bit are

checked for success

If the Byte Write AND Erase Status bits are set to ‘‘1’’s

during a block erase attempt an improper command se-

quence was entered Attempt the operation again

If VPP low status is detected the Status Register must be

cleared before another byte write or block erase opera-

tion is attempted

The VPP Status bit unlike an A D converter does not

provide continuous indication of VPP level The WSM in-

terrogates the VPP level only after the byte write or block

erase command sequences have been entered and in-

forms the system if VPP has not been switched on The

VPP Status bit is not guaranteed to report accurate feed-

back between VPPL and VPPH

the Read Array command until the WSM has com-

pleted its operation The Read Array command is

functional when VPP e VPPL or VPPH

Intelligent Identifier Command

The M28F008 contains an intelligent identifier oper-

ation initiated by writing 90H into the Command

User Interface Following the command write a read

cycle from address 00000H retrieves the manufac-

turer code of 89H A read cycle from address 01H

returns the device code of A2H To terminate the

operation it is necessary to write another valid com-

mand into the register Like the Read Array com-

mand the intelligent identifier command is functional

when VPP e VPPL or VPPH

Read Status Register Command

The M28F008 contains a Status Register which may

be read to determine when a byte write or block

erase operation is complete and whether that oper-

ation completed successfully The Status Register

may be read at any time by writing the Read Status

Register command (70H) to the Command User In-

terface After writing this command all subsequent

read operations output data from the Status Regis-

ter until another valid command is written to the

Command User Interface The contents of the

Status Register are latched on the falling edge of OE

or CE whichever occurs last in the read cycle OE or

CE must be toggled to VIH before further reads to

update the Status Register latch The Read Status

Register command functions when VPP e VPPL or

VPPH

Clear Status Register Command

The Erase Status and Byte Write Status bits are set

to ‘‘1’’s by the Write State Machine and can only be

reset by the Clear Status Register Command These

bits indicate various failure conditions (see Table 4)

By allowing system software to control the resetting

of these bits several operations may be performed

(such as cumulatively writing several bytes or eras-

ing multiple blocks in sequence) The Status Regis-

ter may then be polled to determine if an error oc-

curred during that sequence This adds flexibility to

the way the device may be used

Additionally the VPP Status bit (SR 3) MUST be re-

set by system software before further byte writes or

block erases are attempted To clear the Status

Register the Clear Status Register command (50H)

is written to the Command User Interface The Clear

Status Register command is functional when VPP e

VPPL or VPPH

9

9

Share Link: