PSD913F2V-12J1T 데이터 시트보기 (PDF) - STMicroelectronics
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PSD913F2V-12J1T
STMicroelectronics
PSD913F2V-12J1T Datasheet PDF : 109 Pages
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PSD813F2V PSD854F2V
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 3.3 V
NOT FOR NEW DESIGN
FEATURES SUMMARY
■ FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
Figure 1. Packages
■ DUAL BANK FLASH MEMORIES
– UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8)
– UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors)
PQFP52 (M)
– Concurrent operation: READ from one
) memory while erasing and writing the
t(s other
■ UP TO 256 Kbit of SRAM
uc ■ 27 RECONFIGURABLE I/O PORTS
d ■ ENHANCED JTAG SERIAL PORT
ro ■ PLD WITH MACROCELLS
P – Over 3000 Gates of PLD: CPLD and
te DPLD
le – CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
so – DPLD - user defined internal chip select
b decoding
O ■ 27 INDIVIDUALLY CONFIGURABLE I/O
- PORT PINS
) The can be used for the following functions:
t(s – MCU I/Os
c – PLD I/Os
du – Latched MCU address output
ro – Special function I/Os.
P – 16 of the I/O ports may be configured as
open-drain outputs.
te ■ IN-SYSTEM PROGRAMMING (ISP) WITH
le JTAG
o– Built-in JTAG compliant serial port allows
s full-chip In-System Programmability
Ob– Efficient manufacturing allow easy
PLCC52 (J)
TQFP64 (U)
■ HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 1,000 Erase/WRITE Cycles of PLD
product testing and programming
– 15 Year Data Retention
– Use low cost FlashLINK cable with PC
■ 3.3V±10% SINGLE SUPPLY VOLTAGE
■ PAGE REGISTER
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
■ STANDBY CURRENT AS LOW AS 25µA
■ Packages are ECOPACK®
■ PROGRAMMABLE POWER MANAGEMENT
May 2009
Doc ID 10552 Rev 3
This is information on a product still in production but not recommended for new designs.
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