271092-005 데이터 시트보기 (PDF) - Intel
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271092-005 Datasheet PDF : 29 Pages
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M80C287
Protected Mode Format
15
7
0
Control Word
a0
Status Word
a2
Tag Word
a4
IP Offset
a6
CS Selector
a8
Operand Offset
aA
Operand Selector
aC
15
IP 19 16
OP 19 16
Real-Address Mode Format
7
Control Word
0
a0
Status Word
a2
Tag Word
a4
Instruction Pointer 15 0
a6
0
OPCODE 10 0
a8
Operand Pointer 15 0
aA
0 0 0 0 0 0 0 0 0 0 0 0 aC
Figure 6 Protected Mode Instruction and Data
Pointer Image in Memory
Figure 7 Real Mode Instruction and Data
Pointer Image in Memory
Table 6 CPU Interrupt Vectors Reserved for NPX
Interrupt
Number
Cause of Interrupt
7
In a system with a CPU that has control registers an ESC instruction was encountered when
EM or TS of CPU control register zero (CR0) was set EM e 1 indicates that software
emulation of the instruction is required When TS is set either an ESC or WAIT instruction
causes interrupt 7 This indicates that the current NPX context may not belong to the current
task
9
In a protected-mode system an operand of a coprocessor instruction wrapped around an
addressing limit (0FFFFH for expand-up segments zero for expand-down segments) and
spanned inaccessible addresses (See Note) The failing numerics instruction is not restartable
The address of the failing numerics instruction and data operand may be lost an FSTENV does
not return reliable addresses The segment overrun exception should be handled by executing
an FNINIT instruction (i e an FINIT without a preceding WAIT) The exception can be avoided
by never allowing numerics operands to cross the end of a segment
13
In a protected-mode system the first word of a numeric operand is not entirely within the limit
of its segment The return address pushed onto the stack of the exception handler points at the
ESC instruction that caused the exception including any prefixes The M80C287 has not
executed this instruction the instruction pointer and data pointer register refer to a previous
correctly executed instruction
16
The previous numerics instruction caused an unmasked exception The address of the faulty
instruction and the address of its operand are stored in the instruction pointer and data pointer
registers Only ESC and WAIT instructions can cause this interrupt The CPU return address
pushed onto the stack of the exception handler points to a WAIT or ESC instruction (including
prefixes) This instruction can be restarted after clearing the exception condition in the NPX
FNINIT FNCLEX FNSTSW FNSTENV and FNSAVE cannot cause this interrupt
NOTE
An operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near
the largest valid address in the segment Because of the wrap-around the beginning and ending addresses of such an
operand will be at opposite ends of the segment There are two ways that such an operand may also span inaccessible
addresses 1) if the segment limit is not equal to the addressing limit (e g addressing limit is FFFFH and segment limit is
FFFDH) the operand will span addresses that are not within the segment (e g an 8-byte operand that starts at valid offset
FFFCH will span addresses FFFC–FFFFH and 0000– 0003H however addresses FFFEH and FFFFH are not valid because
they exceed the limit) 2) if the operand begins and ends in present and accessible segments but intermediate bytes of the
operand fall in a not-present segment or page or in a segment or page to which the procedure does not have access rights
Interrupt Description
CPU interrupts are used to report exceptional condi-
tions while executing numeric programs in either real
or protected mode Table 6 shows these interrupts
and their functions
Exception Handling
The M80C287 detects six different exception condi-
tions that can occur during instruction execution Ta-
ble 7 lists the exception conditions in order of prece-
dence showing for each the cause and the
9
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