PT2579 데이터 시트보기 (PDF) - Princeton Technology

부품명

상세내역

제조사

PT2579

RDS Demodulator IC

Princeton Technology 

Tel: 886-2-66296288

Fax:886-2-29174598

URL:http://www.princeton.com.tw

RDS Demodulator IC

PT2579

FUNCTION DESCRIPTION

PT2579 is a demodulator chip specially designed for radio data system applications. It provides 57KHz

bandpass filter and a digital demodulator to regenerate the RDS data stream out of the multiplex signal

(MPX). PT2579 consists of the Filter and Digital Sections.

FILTER SECTION

The MUX Signal is band limited by a second order anti-aliasing filter and fed through a 57KHz 8th order

bandpass filter with a 3KHz bandwidth. This separates the RDS signals. This filter uses switch

capacitor technique and uses a clock frequency of 541.5KHz which is derived from the 4.332/8.664

MHz crystal oscillator. The signal is then fed into the reconstruction filter to smooth the sampled and

filtered RDS signal before it is outputted on the SCOUT pin. The signal is AC-coupled to the

comparator pin (CIN). The comparator uses a frequency of 228KHz (synchronized by the 57KHz of the

demodulator).

DIGITAL SECTION

The Costas Loop Circuit together with the carrier regeneration demodulates the internal coupled

digitized signal. The suppressed carrier is recovered from the 2 sidebands (Costas Loop). The

demodulated signal is low-pass filtered in such a way that the over all pulse shape (transmitter and

receiver) approaches a cosinusoidal form in conjunction with the following integrate and dump circuit.

The data spectrum shaping is divided into two equal parts and handled in the transmitter and in the

receiver. Ideally, the data filtering should be equal in both of these parts. The overall data channel

spectrum shaping of the transmitter and the receiver is approximately 100% roll off.

Theintegrate and dump circuit performs anintegration over a clock period. This results in a

demodulation and valid RDS signal in form of biphase symbols being outputted from the integrate and

dump circuit. The final stages of the RDS data processing are the biphase symbol decoding and the

differential decoding. After synchronization by the data clock RDCL, data appears on the RDDA output.

The output of the biphase symbol decoder is evaluated by a special circuit to provide an indication of

good data (QUAL=HIGH) or corrupt data (QUAL=LOW).

PT2579 V1.6

-4-

May, 2008

Share Link: