QL4016-4PLI 데이터 시트보기 (PDF) - Unspecified

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QL4016-4PLI

16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM

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QL4016 QuickRAM Data Sheet Rev I

Symbol

tI/O

tISU

tIH

tIOCLK

tIORST

tIESU

tIEH

Table 7: I/O Cell Input Delays

Parameter

Propagation Delays (ns)

Fanouta

1 2 3 4 8 10

Input Delay (bidirectional pad)

1.3 1.6 1.8 2.1 3.1 3.6

Input Register Set-Up Time

3.1 3.1 3.1 3.1 3.1 3.1

Input Register Hold Time

0.0 0.0 0.0 0.0 0.0 0.0

Input Register Clock to Q

0.7 1.0 1.2 1.5 2.5 3.0

Input Register Reset Delay

0.6 0.9 1.1 1.4 2.4 2.9

Input Register Clock Enable Set-Up Time

2.3 2.3 2.3 2.3 2.3 2.3

Input Register Clock Enable Hold Time

0.0 0.0 0.0 0.0 0.0 0.0

a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and

TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature

settings as specified in the Operating Range.

Table 8: I/O Cell Output Delays

Symbol

Parameter

tOUTLH

tOUTHL

tPZH

tPZL

tPHZ

tPLZ

Output Delay Low to High

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-statea

Output Delay High to Tri-statea

Propagation Delays (ns)

Output Load Capacitance (pF)

3

50

75 100 150

2.1 2.5 3.1 3.6 4.7

2.2 2.6 3.2 3.7 4.8

1.2 1.7 2.2 2.8 3.9

1.6 2.0 2.6 3.1 4.2

2.0

-

-

-

-

1.2

-

-

-

-

a. These loads are used for tPXZ (see Figure 5)

1ΚΩ

tPHZ

5 pF

1ΚΩ

tPLZ

5 pF

Figure 5: Loads Used for tPXZ

© 2002 QuickLogic Corporation

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