QT60320D 데이터 시트보기 (PDF) - Quantum Research Group
부품명
상세내역
제조사
QT60320D Datasheet PDF : 14 Pages
| |||
2 - CIRCUIT
Figure 2-1 Basic QT60320D Circuit
SPECIFICS
V cc
A basic QT60320D circuit is
shown in Figure 2-1.
2.1 SIGNAL PATH
The QT60320D requires an
external sampling capacitor,
two Cz capacitors, an amplifier,
some analog switches, and an
R2R ladder DAC to operate.
The Cs capacitor performs the
charge integration function by
collecting charge coupled
though a selected key during
the dV/dt of the rising edge of
an 'X' scan line. The charge is
sampled 'n' times during the
course of a burst of switching
cycles of length 'n'. As the
burst progresses the charge on
Cs increases in a staircase
fashion (Figure 1-4).
At the burst's end the voltage
D S 18 11
UART IN
UART OUT
5 17 27 29 38
V V V VV
4 Rst
9
10 Rx
Tx
33
I1
34 I2
35
36 I3
I4
X1 40
41
X2 42
X3 43
X4
X5 44
1
X6 2
X7
X8 3
11
12 O1
O2
13 O3
14 O4
23
24 O5
O6
25
O7
26 O8
8
XT1
7
XT2
8MHz
V cc
CAL LED
15
L1
16
L2
R2R dac 100K
19
YS1
YS2 20
21
YS3
YS4 22
C6 (Cz1) 820pF
32
CC1
C7 (Cz2) 820pF
31
CC2
CS 30
BSN20
37
+
AIN
_
R3 68K
_
+
TL C22 72
STAT LED
GGGG
6 18 28 39
R6 10K
R4 100K
Keymatrix
Y4 Y3 Y2 Y1
R5 10K
C5 (Cs)
1 5nF
74 AC 04
on Cs, which is on the order of
a few tenths of a volt, is
amplified by a gain circuit which includes an offset current between 0 and 5 volts. Between bursts the Cs reset mosfet is
from the R2R ladder DAC driven by the X drive lines. The activated to reset the Cs capacitor to ground.
offset current from the R2R ladder repositions the output of Gain is directly controlled by burst length 'n', amplifier gain
the amplifier chain to coincide as closely as possible with the Av, and the values of Cs, Cz1 and Cz2. Only 'n' can be
center span of the 60320's ADC, which can convert voltages adjusted on a key by key basis whereas Av and the
capacitances can only be adjusted
Figure 2-2 Improved Circuit to Suppress Water Films
for all keys. The amplifier should
typically have a total positive gain
Vcc
D S 18 11
UART IN
UART OUT
5 17 27 29 38
V V V VV
4
R st
9 Rx
10
Tx
33 I1
34
35 I2
I3
36
I4
40
X2 41
X3 42
43
X4 44
X5 1
X6
X7 2
3
X8
11
12 O1
O2
13 O3
14
O4
23
24 O5
25 O6
O7
26 O8
8 XT1
R2R dac 100K
19
YS1
YS2 20
21
YS3
22
YS4
C6 (Cz1) 820pF
CC 1 32
C 7 (Cz2) 820p F
7
XT2
31
CC 2
8MH z
Vcc
CAL L ED
15 L1
30
CS
BS N 20
16 L2
AIN 37
+
_
STAT LED
GGGG
6 18 28 39
22V10
R3 68K
_
+
TLC2272
R6 10K
Keym atr ix
Y4 Y3 Y2 Y1
E I /O
I/O I /O
I/O
E
E
QS3125
E I /O
I/O I /O
I/O
Ct
Rt
R5 1 0K
C5 (Cs)
15nF
of 100 +/- 20%..
If there is a large amount of
coupling between X and Y lines,
and where burst length 'n' is set to
a high number, charge
accumulation on Cs may reach a
point where the ladder DAC can no
longer offset the signal back into
the ADC's usable range. In this
case the circuit will employ one or
two of the Cz capacitors to 'knock
back' or cancel the charge
accumulated on Cs; each Cz will
cancel charge in a discrete step as
required.
R4 100K
LQ
5
QT60320D R1.11/12.07.03
Share Link: 