R4430PCP10MCM 데이터 시트보기 (PDF) - Aeroflex Corporation
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R4430PCP10MCM Datasheet PDF : 11 Pages
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Clock/Control Interface Signals
TClock(1:0)
O Transmit clocks : Two identical transmit clocks that
establish the system interface frequency
RClock(1:0)
O Receive clocks: Two identical receive clocks that estab-
lish the system interface frequency
MasterClock
I Master clock: Master clock input establishes the pro-
cessor operating frequency
Masterout
O Master clock out: Master clock output aligned with
MasterClock
SyncOut
O Synchronization clock out: Synchronization clock out-
put must be connected to SyncIn through an intercon-
nect that models the interconnect between MasterOut,
TClock, RClock, and the external agent.
SyncIn
I Synchronization clock in: Synchronization clock input
IOOut
O I/O output: Output slew rate control feedback loop out-
put. Must be connected to IOIn through a delay loop
that models the I/O path from the processor to an
external agent.
IOIn
I I/O input: Output slew rate control feedback loop input
(see IOOut)
Fault*
O Fault: The processor asserts Fault to indicate a mis-
match output of boundry comparators
VccP
I Quiet Vcc for the PLL: Quiet Vcc for the internal phase
lock loop
VssP
I Quiet Vss for the PLL: Quiet Vss for the internal phase
lock loop
Status(7:0)
O Status: An 8 bit bus that indicates the current operation
status of the processor
VccSense
I/O Vcc sense: This is a special pin used for testing and
characterization. The voltage at this pin directly shows
the behavior of the on chip Vcc.
VssSense
I/O Vss sense: VssSense provides a separate, direct connec-
tion fron the on-chip Vss node to a package pin without
attaching to the in-package ground planes. VssSence
should be connected to Vss in functional system
designs.
6
SCD4430 Rev A 11/18/96
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