EVRDA012M4-HD 데이터 시트보기 (PDF) - Unspecified

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EVRDA012M4-HD

12 Bit 1.3 GS/s 4:1 MUXDAC

Unspecified 

RDA012M4 DATASHEET

DS_0012PB1-2805

Signal Description

HIGH SPEED INPUT CLOCK.

The RDA012M4 high-speed clock input is

differential and can be driven from typical ECL

circuits. Also a differential sinusoidal clock can

be used. The HCLKIP and HCLKIN inputs, are

internally terminated with 50 Ω to VTT which

should be connected to a well decoupled –2.0

volt supply. Since the MUXDAC's output phase

noise is directly related to the input clock noise

and jitter, a low-jitter clock source is ideal. The

internal clock driver generates very little added

jitter (~100fs). A 500MHz MUXDAC output

demands a white noise induced clock jitter of

less than 250fs for a 10-bit equivalent, 62dB

SNDR.

DATA INPUT.

The data inputs are 3.3V NMOS-compatible.

The data is interleaved according to significant

bit. For example, consecutive data pins will

occur as DIA0, DIB0, DIC0, DID0, DIA1, DIB1,

etc.

OUTPUT CLOCK.

Output clock LCLKOP and LCLKON are

supplied for the DSP/FPGA/ASIC. They are

LVDS compliant and needs to be terminated

with a 100Ω resistor in front of the receiving

buffer or the receiving pins of the ASIC/DSP.

For application convenience, the data input's

setup and hold time is specified with respect to

the LCLKO. It should be noted that LCLKOP and

LCLKON are driven by the MUXDAC and the

waveforms of these signals are better defined at

the receiver end; that is, near the ASIC/DSP

chip that provides the input data for the

MUXDAC. The system designer should

consider the delay associated with the signal

routing in the system's timing budget.

In figure 6, the setup and hold time of the LCLK

to data transition are defined at the MUXDAC

side. Data transitions of the data input have to

occur during the "Valid Data Transition Window."

The timing margin seen from the MUXDAC is

TP-TS where TP is the LCLKO period and TS is

the setup time, assuming that the ASIC chip

takes LCLKO as the clock input and its outputs

are latched at the falling edge of the clock.

From the ASIC/DSP end, however, the timing

margin is decreased by the amount equal to the

sum of the data delay and clock delay between

the two chips, as noted in the lower part of the

diagram.

ANALOG OUTPUT.

The outputs OUTP and OUTN should both be

connected though a 50 Ω resistor to ground.

This will give a full-scale amplitude of 0.6 volt

(both outputs must be terminated), 1.2 volt

differentially. The output common mode can be

changed by terminating the load resistors to a

different voltage. However, the device is

optimized to perform best when connected to a

voltage between 0 and 1 volt. For reliable

operation, the output termination voltage should

not exceed 3 volts.

REFERENCE.

VREFA is provided for added control of the full-

scale amplitude output. The internal reference

circuit is designed to provide -2.0 volts, which

can change up to ±5% as the supply voltage

and/or operating temperature changes. If the

user prefers accurately control the output full-

scale signal, an external voltage reference with

low output impedance to override the internal

reference should be used. The output full-scale

voltage follows the relationship VFS = 0.3xVREF.

Note that the MUXDAC is optimized to have the

best performance with a reference voltage of -

2.0 volts. The output resistance of the reference

node is 560 Ω ±10%. VREFD allows adjusting of

the digital circuitry bias point for varying input

voltage swings. In most cases, VREFD should

be bypassed to GND.

Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice.

The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.

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