ADSP-21MOD980N-000 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21MOD980N-000

MultiPort Internet Gateway Processor

Analog Devices 

PRELIMINARY TECHNICA L DATA

For current information contact Analog Devices at (800) ANALOGD

ADSP-21mod980N

T1/E1

LINE

INTERFACE

T1/E1

LINE

INTERFACE

SPORT

21mod980N

SPORT

21mod980N

ST/CNTL IDMA

ST/CNTL IDMA

T1/E1

LINE

INTERFACE

SPORT

21mod980N

ST/CNTL IDMA

Figure 3. Multichannel Modem Configuration

CLOCK SIGNALS

The ADSP-21mod980N is clocked by a TTL-compatible

clock signal that runs at half the instruction rate; a 40 MHz

input clock yields a 12.5 ns processor cycle, which is equiv-

alent to 80 MHz. Normally, instructions are executed in a

single processor cycle. All device timing is relative to the

internal instruction clock rate, which is indicated by the

CLKOUT signal when enabled. The clock input signal is

connected to the processor’s CLKIN input.

The CLKIN input cannot be halted, changed during oper-

ation, or operated below the specified frequency during

normal operation. The only exception is while the processor

is in the power down state. For additional information, refer

to Chapter 9, ADSP-2100 Family User’s Manual for a

detailed explanation of this power down feature.

REV. PrB 6/2001

9

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