RMLA3565C-TB 데이터 시트보기 (PDF) - Fairchild Semiconductor
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RMLA3565C-TB Datasheet PDF : 5 Pages
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Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE
The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a surface mount
package. It may be noted that the chip is a fully monolithic single ended two stage amplifier for 3.5 to 6.5 GHz applications.
Figure 1 shows the functional block diagram of the packaged product.
Test Fixture
Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture schematic showing
external bias components is shown in Figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the
schematic diagram. Typical performance of the test fixture is shown in the performance data section. The following should
be noted:
(1) Package pin designations are shown in Figure 2.
(2) Vd is the drain voltage (positive) applied at the pins of the package.
(3) Vdd is the positive supply voltage at the evaluation board terminal.
GROUND GROUND
Pin# 5 Pin# 1, 3, 4, 6, 9, 10, 11, 13
MMIC CHIP
GROUND
Pin# 7
RF IN
Pin# 8
RF OUT
Pin# 2
Vd
Pin# 12
Figure 1. Functional Block Diagram
Top View
0.200 SQ.
654
Bottom View
456
7
0.030
8
9
3
0.015
3
2
2
1
1
0.020
0.011
10 11 12
7
8
9
12 11 10
0.041
0.010
Plastic Lid
0.230
0.246
0.282
Dimensions in inches
0.075 MAX
Side Section
Pin
Description
1
GND
2
RF Out
3
GND
4
GND
5
GND
6
GND
7
GND
8
RF In
9
GND
10
GND
11
GND
12
Vd
13
GND
(Package Base)
Figure 2. Package Outline Dimensions
©2004 Fairchild Semiconductor Corporation
RMLA3565C Rev. C
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