RT8061A 데이터 시트보기 (PDF) - Richtek Technology
부품명
상세내역
제조사
RT8061A Datasheet PDF : 12 Pages
| |||
RT8061A
where LIR is the ratio of the peak-to-peak ripple current to
the average inductor current.
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
(IPEAK) :
IPEAK
=
ILOAD(MAX)
+
⎛⎜⎝
LIR
2
× ILOAD(MAX)
⎞⎟⎠
The calculation above serves as a general reference. To
further improve transient response, the output inductor
can be further reduced. This relation should be considered
along with the selection of the output capacitor.
Input Capacitor Selection
High quality ceramic input decoupling capacitor, such as
X5R or X7R, with values greater than 20μF are
recommended for the input capacitor. The X5R and X7R
ceramic capacitors are usually selected for power regulator
capacitors because the dielectric material has less
capacitance variation and more temperature stability.
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Generally, selecting an
input capacitor with voltage rating 1.5 times greater than
the maximum input voltage is a conservatively safe design.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
IIN_RMS = ILOAD ×
VOUT
VIN
× ⎛⎜⎝1−
VOUT
VIN
⎞⎟⎠
The next step is selecting a proper capacitor for RMS
current rating. One good design is using more than one
capacitor with low Equivalent Series Resistance (ESR) in
parallel to form a capacitor bank.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
ΔVIN
=
IOUT(MAX) × 0.25
CIN × fSW
For example, if IOUT(MAX) = 3A, CIN = 20μF, fSW = 1MHz,
the input voltage ripple will be 37.5mV.
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
VP-P
= LIR ×ILOAD(MAX)
× ⎛⎜⎝ESR +
1
8 × COUT
× fSW
⎞⎟⎠
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG)
can be calculated by the following equation :
VSAG = ΔILOAD ×ESR
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, the ESL contributes to part of the voltage sag.
Using a capacitor with low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using a single capacitor for the same total ESR.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
to obtain better transient performance.
Power Good Output (PGOOD)
PGOOD is an open-drain type output and requires a pull-
up resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when the output
voltage rises above 90% of nominal regulation point. The
PGOOD signal goes low if the output is turned off or is
10% below its nominal regulation point.
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS8061A-04 September 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
Share Link: 