RT8857 데이터 시트보기 (PDF) - Richtek Technology

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RT8857

4/3/2/1-Phase PWM Controller with Embedded Drivers for CPU Core Power Supply

Richtek Technology 

RT8857/A

VTT

VCC12

VCC5

VDAC

0.85V

9.6V

4.6V

SS

SSQ

PWRGD

T1

T2

T3 T4 T5

Figure 5. Soft Start Waveforms

SS

SSQ

VBOOT

VOUT will trace VEAP which is equal to “VSSQ − VADJ”.

VADJ is a small voltage signal which is proportional to

IOUT. This voltage is used to generate loadline and will be

described later. T1 is the delay time from power_on_reset

state to the beginning of VOUT rising.

T1 = 1600μs + 0.6V x CSS / ISS1

(1)

T2 is the soft start time from VOUT = 0 to VOUT = VBOOT.

T2 = VBOOT x CSS / ISS1

(2)

T3 is the dwelling time for VOUT = VBOOT. T3 = 800us.

T4 is the soft start time from VOUT = VBOOT to VOUT = VDAC.

T4 ~= |VDAC - VBOOT| x CSS/ISS1

(3)

T5 is the power good delay time, T5 ~= 1600us.

Dynamic VID

The RT8857/A can accept VID input changing while the

controller is running. This allows the output voltage (VOUT)

to change while the DC/DC converter is running and

supplying current to the load. This is commonly referred

to as VID on-the-fly (OTF). A VID OTF can occur under

either light or heavy load conditions. The CPU changes

the VID inputs in multiple steps from the start code to the

finish code. This change can be positive or negative.

Theoretically, VOUT should follow VDAC which is a staircase

waveform. In RT8857/A, as mentioned in soft start session,

VDAC slew rate is limited by ISS2/CSS when PWRGD = H.

This slew rate limiter works as a low pass filter of VDAC

and makes the bandwidth of VDAC waveform finite. By

smoothening VDAC staircase waveform, VOUT will no longer

overshoot or undershoot. On the other hand, CSS will

increase the settling time of VOUT during VID OTF. In most

cases, 1nF to 30nF ceramic capacitor is suitable for CSS.

DS8857/A-01 April 2011

Output Voltage Differential Sensing

The RT8857/A uses differential sensing by a high gain

low offset ErrorAmp. The CPU voltage is sensed between

the FB and FBRTN pins. A resistor (RFB) connects FB pin

and the positive remote sense pin of the CPU (VCCP).

FBRTN pin connects to the negative remote sense pin of

CPU (VCCN) directly. The ErrorAmp compares EAP (=

VDAC −VADJ) with the VFB to regulate the output voltage.

No-Load Offset

In Figure 6, IOFSN or IOFSP are used to generate no-load

offset. Either IOFSN or IOFSP is active during normal operation.

It should be noted that users can only enable one polarity

of no-load offset. Do not connect OFS pin to GND and to

VCC5 at the same time. Connect a resistor from OFS pin

to GND to activate IOFSN. IOFSN flows through RADJ from

ADJ pin to GND. In this case, negative no-load offset voltage

(VOFSN) is generated.

VOFSN = IOFSN x RADJ = 0.8 x RADJ/ROFS

(4)

Connect a resistor from OFS pin to VCC5 to activate IOFSP.

IOFSP flows through RFB from the VCCP to FB pin. In this

case, positive no-load offset voltage (VOFSP) is generated.

When positive no-load offset is selected, the RT8857/A

will generate another internal 8uA current source to

eliminate dead zone problem of droop function. This 8uA

current will be injected into ADJ resistors, producing a

small initial negative no-load offset. Therefore, when OFS

pin is connected to VCC5 through a resistor, the positive

no-load offset can be calculated as :

VOFSP = IOFSP ×RFB − 8uA ×RADJ

=

6.4

×

RFB

ROFS

− 8uA ×RADJ

(5)

RT8857/A provides wide range no-load positive offset for

over-clocking applications. The IOFSP capability can supply

from 30uA to 640uA, which means in Equation (5), ROFS

can range from 240kΩ to 10kΩ. Other resistances of ROFS

exceeding this range can also provide no-load positive

offset but cannot be guaranteed by Equation (5).

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