RT9005B 데이터 시트보기 (PDF) - Richtek Technology
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RT9005B Datasheet PDF : 10 Pages
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RT9005A/B
Preliminary
Application Information
Thermal Consideration
RT9005A/B regulators have internal thermal limiting
circuitry designed to protect the device during overload
conditions. For continued operation, do not exceed
maximum operation junction temperature 125°C. The
power dissipation definition in device is :
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = ( TJ(MAX) -TA ) /θJA
Where TJ(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and
the θJA is the junction to ambient thermal resistance. The
junction to ambient thermal resistance (θJA is layout
dependent) for SOP-8 package (Exposed Pad) is 75°C/
W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by following formula :
PD(MAX) = (125°C - 25°C) / 75°C/W = 1.33W
Figure 2 show the package sectional drawing of SOP-8
(Exposed Pad). Every package has several thermal
dissipation paths. As show in Figure 2, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pad). The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.
Ambient
Molding Compound
Gold Line
Lead Frame
RGOLD-LINE RLEAD FRAME RPCB
path 1
Junction
RDIE RDIE-ATTACH RDIE-PAD
RPCB
path 2
Case
(Exposed Pad)
Ambient
RMOLDING-COMPOUND
path 3
Figure 2. Thermal Resistance Equivalent Circuit
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design has been decided. If
possible, it's useful to increase thermal performance by
the PCB design. The thermal resistance can be decreased
by adding copper under the expose pad of SOP-8
package.
About PCB layout, the Figure 3 show the relation between
thermal resistance θJA and copper area on a standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board at
TA = 25°C.We have to consider the copper couldn't stretch
infinitely and avoid the tin overflow. We use the “dog-bone”
copper patterns on the top layer as Figure 4.
As shown in Figure 5, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard SOP-8
(Exposed Pad) pad of 2 oz. copper (Figure 5.a), θJA is
75°C/W. Adding copper area of pad under the SOP-8
(Exposed Pad) (Figure 5.b) reduces the θJA to 64°C/W.
Even further, increasing the copper area of pad to 70mm2
(Figure 5.e) reduces the θJA to 49°C/W.
Die Pad
Case (Exposed Pad)
Figure 1. SOP-8 (Exposed Pad) Package Sectional
Drawing
www.richtek.com
8
DS9005A/B-01 September 2007
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