RT8223L 데이터 시트보기 (PDF) - Richtek Technology

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RT8223L

High Efficiency, Main Power Supply Controller for Notebook Computer

Richtek Technology 

RT8223L/M

Functional Pin Description

Pin No.

1

2

Pin Name

ENTRIP1

FB1

Pin Function

Channel 1 Enable and Current Limit Setting Input. Connect a resistor to GND to

set the threshold for channel 1 synchronous RDS(ON) sense. The GND − PHASE1

current limit threshold is 1/10th the voltage seen at ENTRIP1 over a 0.515V to 3V

range. There is an internal 10μA current source from VREG5 to ENTRIP1. Leave

ENTRIP1 floating or drive it above 4.5V to shut down channel 1.

SMPS1 Feedback Input. Connect FB1 to a resistive voltage divider from VOUT1

to GND to adjust output from 2V to 5.5V.

3

REF

2V Reference Output. Bypass to GND with a minimum 0.22μF capacitor. REF can

source up to 100μA for external loads. Loading REF degrades FBx and output

accuracy according to the REF load-regulation error.

Frequency Selectable Input for VOUT1/VOUT2 respectively.

4

TONSEL

400kHz/500kHz : Connect to VREG5 or VREG3

300kHz/375kHz : Connect to REF

200kHz/250kHz : Connect to GND

5

FB2

SMPS2 Feedback Input. Connect FB2 to a resistive voltage divider from VOUT2

to GND to adjust output voltage from 2V to 5.5V.

Channel 2 Enable and Current Limit Setting Input. Connect a resistor to GND to

set the threshold for channel 2 synchronous RDS(ON) sense. The GND − PHASE2

6

ENTRIP2

current limit threshold is 1/10th the voltage seen at ENTRIP2 over a 0.515V to 3V

range. There is an internal 10μA current source from VREG5 to ENTRIP2. Leave

ENTRIP1 floating or drive it above 4.5V to shut down channel 2.

7

VOUT2

Bypass Pin for SMPS2. Connect to the SMPS2 output to bypass efficient power

for VREG3 pin. VOUT2 is also for the SMPS2 output soft-discharge.

8

VREG3

3.3V Linear Regulator Output.

9

BOOT2

Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor

according to the typical application circuits.

10

UGATE2

Upper Gate Driver Output for SMPS2. UGATE2 swings between PHASE2 and

BOOT2.

Switch Node for SMPS2. PHASE2 is the internal lower supply rail for the

11

PHASE2

UGATE2 high side gate driver. PHASE2 is also the current-sense input for the

SMPS2.

12

LGATE2

Lower Gate Driver Output for SMPS2. LGATE2 swings between GND and

VREG5.

13

EN

Master Enable Input. The REF/VREG5/VREG3 are enabled if it is within logic

high level and disabled if it is less than the logic low level.

Operation Mode Selectable Input.

14

SKIPSEL

Connect to VREG5 or VREG3 : Ultrasonic Mode

Connect to REF : PWM Mode

Connect to GND : DEM Mode

16

VIN

Supply Input for 5V/3.3V LDO and Feed Forward On-Time circuitry.

17

VREG5

5V Linear Regulator Output. VREG5 is also the supply voltage for the lower gate

driver and analog supply voltage for the device.

18

NC

(RT8223L)

ENC

No Internal Connection.

SMPS Enable Input. Pull up to VREG3 or VREG5 to turn on both switch channels.

(RT8223M) Short to GND to shutdown them.

19

LGATE1

Lower Gate Driver Output for SMPS1. LGATE1 swings between GND and

VREG5.

www.richtek.com

4

To be continued

DS8223L/M-04 April 2011

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