IS61SF12836-8.5BI 데이터 시트보기 (PDF) - Integrated Circuit Solution Inc
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IS61SF12836-8.5BI
Integrated Circuit Solution Inc
IS61SF12836-8.5BI Datasheet PDF : 16 Pages
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15$ 5. &!
15$ 5. &!$
128K x 32, 128K x 36 SYNCHRONOUS
.LOW-THROUGH STATIC RAM
.EATURES
.ast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,
and 12 ns
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data
inputs and control signals
PentiumTM or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin LQ.P and
119-pin PBGA package
Single +3.3V +10%, -5% power supply
Power-down snooze mode
DESCRIPTION
The 1+51 IS61S.12832 and IS61S.12836 are high-speed
synchronous static RAM designed to provide a burstable, high-
performance for high speed networking and communication
applications. It is organized as 131,072 words by 32 bits or 36
bits, fabricated with 1+51's advanced CMOS technology. The
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,
BW4 controls DQd, conditioned by BWE being LOW. A LOW
on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61S.12832 and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
.AST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
.renquency
7.5
8
8.5
10
12
7.5
8
8.5
10
12
8.5
10
11
15
15
117
100
90
66
66
Units
ns
ns
MHz
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
1
SSR014-0C
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