RT9602 데이터 시트보기 (PDF) - Richtek Technology
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RT9602 Datasheet PDF : 11 Pages
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RT9602
Application Information
The RT9602 has power on protection function which held
UGATE and LGATE low before VCC up cross the rising
threshold voltage. After the initialization, the PWM signal
takes the control. The rising PWM signal first forces the
LGATE signal turns low then UGATE signal is allowed to
go high just after a non-overlapping time to avoid shoot-
through current. The falling of PWM signal first forces
UGATE to go low. When UGATE and PHASE signal reach
a predetermined low level, LGATE signal is allowed to turn
high. The non-overlapping function is also presented
between UGATE and LGATE signal transient.
The PWM signal is recognized as high if above rising
threshold and as low if below falling threshold. Any signal
level in this window is considered as tri-state, which causes
turn-off of both high side and low-side MOSFET. When
PWM input is floating (not connected), internal divider will
pull the PWM to 1.9V to give the controller a recognizable
level. The maximum sink/source capability of internal PWM
reference is 60μA.
The PVCC pin provides flexibility of both high side and low
side MOSFET gate drive voltages. If 8V, for example, is
applied to PVCC, then high side MOSFET gate drive is 8V
to 1.5V (approximately, internal diode plus series resistance
voltage drop). The low side gate drive voltage is exactly
8V.
The RT9602 implements a power on over-voltage protection
function. If the PHASE voltage exceeds 1.5V at power on,
the LGATE would be turn on to pull the PHASE low until
the PHASE voltage goes below 1.5V. Such function can
protect the CPU from damage by some short condition
happened before power on, which is sometimes
encountered in the M/B manufacturing line.
Driving power MOSFETs
The DC input impedance of the power MOSFET is
extremely high. When Vgs at 12V (or 5V), the gate draws
the current only few nanoamperes. Thus once the gate
has been driven up to “ON”ON level, the current could be
negligible.
However, the capacitance at the gate to source terminal
should be considered. It requires relatively large currents
to drive the gate up and down 12V (or 5V) rapidly. It also
required to switch drain current on and off with the required
speed. The required gate drive currents are calculated as
follows.
D1
d1
s1
Vi
L
VO
Cgd1
Cgs1
Igd1
Igs1
Ig1
g1 g2
Ig2 Igd2
Igs2
Cgd2 d2
D2
Cgs2
s2
GND
Vg1 Vphase
+12V
t
Vg2
+12V
t
Figure1. The gate driver must supply Igs to Cgs and Igd to Cgd
In Figure 1, the current Ig1 and Ig2 are required to move the
gate up to 12V.The operation consists of charging Cgd and
Cgs. Cgs1 and Cgs2 are the capacitances from gate to source
of the high side and the low side power MOSFETs,
respectively. In general data sheets, the Cgs is referred as
“Ciss” which is the input capacitance. Cgd1 and Cgd2 are
the capacitances from gate to drain of the high side and
the low side power MOSFETs, respectively and referred to
the data sheets as "Crss," the reverse transfer capacitance.
For example, tr1 and tr2 are the rising time of the high side
and the low side power MOSFETs respectively, the required
current Igs1 and Igs2, are showed below
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DS9602-08 March 2007
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