RTL8100CL-LF 데이터 시트보기 (PDF) - Realtek Semiconductor

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RTL8100CL-LF

SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

Offset

0044h-0047h

0048h-004Bh

R/W

R/W

R/W

004Ch-004Fh

R/W

Tag

RCR

TCTR

MPC

0050h

0051h

0052h

0053H

0054h-0057h

R/W

R/W

R/W

-

R /W

9346CR

CONFIG0

CONFIG1

-

TimerInt

0058h

R/W

0059h

R/W

005Ah

R/W

005Bh

-

005Ch-005Dh

R/W

005Eh

R

005Fh

-

0060h-0061h

R

0062h-0063h

R/W

0064h-0065h

R

0066h-0067h

R/W

0068h-0069h

R

006Ah-006Bh

R

006Ch-006Dh

R

006Eh-006Fh

R

0070h-0071h

R/W

0072h-0073h

R

0074h-0075h

R/W

0076-0077h

-

0078h-007Bh

R/W

007Ch-007Fh

R/W

0080h

R/W

0081-0083h

-

0084h

R/W

0085h

R/W

0086h

R/W

0087h

R/W

0088h

R/W

MSR

CONFIG3

CONFIG4

-

MULINT

RERID

-

TSAD

BMCR

BMSR

ANAR

ANLPAR

ANER

DIS

FCSC

NWAYTR

REC

CSCR

-

PHY1_PARM

TW_PARM

PHY2_PARM

-

CRC0

CRC1

CRC2

CRC3

CRC4

Single-Chip Fast Ethernet Controller

RTL8100C & RTL8100CL

Datasheet

Description

Receive (Rx) Configuration Register.

Timer CounT Register.

This register contains a 32-bit general-purpose timer. Writing any

value to this register will reset the original timer and start a count

from zero.

Missed Packet Counter.

Indicates the number of packets discarded due to Rx FIFO

overflow. It is a 24-bit counter. After s/w reset, MPC is cleared.

Only the lower 3 bytes are valid.

When any value is written, MPC will be reset also.

93C46 Command Register.

Configuration Register 0.

Configuration Register 1.

Reserved.

Timer Interrupt Register.

Once having written a non-zero value to this register, the Timeout

bit of the ISR register will be set whenever the TCTR reaches that

value. The Timeout bit will never be set whilst the TimerInt register

is zero.

Media Status Register.

Configuration register 3.

Configuration register 4.

Reserved.

Multiple Interrupt Select.

PCI Revision ID = 10h.

Reserved.

Transmit Status of All Descriptors.

Basic Mode Control Register.

Basic Mode Status Register.

Auto-Negotiation Advertisement Register.

Auto-Negotiation Link Partner Register.

Auto-Negotiation Expansion Register.

Disconnect Counter.

False Carrier Sense Counter.

N-way Test Register.

RX_ER Counter.

CS Configuration Register.

Reserved.

PHY Parameter 1.

Twister Parameter.

PHY Parameter 2.

Reserved.

Power Management CRC register 0 for wakeup frame 0.

Power Management CRC register 1 for wakeup frame 1.

Power Management CRC register 2 for wakeup frame 2.

Power Management CRC register 3 for wakeup frame 3.

Power Management CRC register 4 for wakeup frame 4.

11

Track ID: JATR-1076-21 Rev. 1.06

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