RTL8100C 데이터 시트보기 (PDF) - Realtek Semiconductor

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RTL8100C

SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

RTL8100C & RTL8100CL

Datasheet

Table of Contents

1. GENERAL DESCRIPTION...............................................................................................................1

2. FEATURES..........................................................................................................................................2

3. BLOCK DIAGRAM............................................................................................................................3

4. PIN ASSIGNMENTS ..........................................................................................................................4

4.1. RTL8100C (QFP) & RTL8100CL (LQFP).....................................................................................4

5. PIN DESCRIPTION............................................................................................................................5

5.1. POWER MANAGEMENT/ISOLATION INTERFACE ................................................................................5

5.2. PCI INTERFACE ................................................................................................................................6

5.3. EPROM/EEPROM INTERFACE/AUX .............................................................................................8

5.4. POWER PINS .....................................................................................................................................8

5.5. LED INTERFACE...............................................................................................................................8

5.6. ATTACHMENT UNIT INTERFACE .......................................................................................................9

5.7. TEST AND OTHER PINS .....................................................................................................................9

5.8. REGISTER DESCRIPTIONS................................................................................................................10

5.9. RECEIVE STATUS REGISTER IN RX PACKET HEADER.....................................................................12

5.10. TRANSMIT STATUS REGISTER (TSD0-3)(OFFSET 0010H-001FH, R/W) ........................................13

5.11. ERSR: EARLY RX STATUS REGISTER (OFFSET 0036H, R) ............................................................14

5.12. COMMAND REGISTER (OFFSET 0037H, R/W) .................................................................................15

5.13. INTERRUPT MASK REGISTER (OFFSET 003CH-003DH, R/W).........................................................15

5.14. INTERRUPT STATUS REGISTER (OFFSET 003EH-003FH, R/W) .......................................................16

5.15. TRANSMIT CONFIGURATION REGISTER (OFFSET 0040H-0043H, R/W)...........................................17

5.16. RECEIVE CONFIGURATION REGISTER (OFFSET 0044H-0047H, R/W).............................................19

5.17. 9346CR: 93C46 COMMAND REGISTER (OFFSET 0050H, R/W) .....................................................22

5.18. CONFIG 0: CONFIGURATION REGISTER 0 (OFFSET 0051H, R/W)................................................23

5.19. CONFIG 1: CONFIGURATION REGISTER 1 (OFFSET 0052H, R/W)................................................23

5.20. MEDIA STATUS REGISTER (OFFSET 0058H, R/W) ..........................................................................24

5.21. CONFIG 3: CONFIGURATION REGISTER3 (OFFSET 0059H, R/W).................................................25

5.22. CONFIG 4: CONFIGURATION REGISTER4 (OFFSET 005AH, R/W)................................................27

5.23. MULTIPLE INTERRUPT SELECT REGISTER (OFFSET 005CH-005DH, R/W).....................................28

Single-Chip Fast Ethernet Controller

iii

Track ID: JATR-1076-21 Rev. 1.06

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