S1M8823 데이터 시트보기 (PDF) - Samsung
부품명
상세내역
제조사
S1M8823 Datasheet PDF : 22 Pages
| |||
S1M8821/22/23
INTERGER RF/IF DUAL PLL
PIN DESCRIPTION
Pin No
(20TSSOP)
Pin No
(24QFN)
Symbol
I/O
Description
1
24
VDD1
-
Power supply voltage input for the RF PLL part. VDD1 must
equal VDD2. In order to reject supply noise, bypass capacitors
must be placed as close as possible to this pin and be
connected directly to the ground plane.
-
1
-
N/C No connection.
2
2
Vp1
-
Power supply voltage input for RF charge pump( ≥ VDD1).
3
3
CPoRF
O Internal RF charge pump output for connection to an external
loop filter whose filtered output drives an external VCO.
4
4
GND
-
Ground for RF digital blocks.
5
5
finRF
I
RF prescaler input. The signal comes from the external VCO.
6
6
finRF
I
The complementary input of the RF prescaler. A bypass
capacitor must be placed as close as possible to this pin and
be connected directly to the ground plane. The bypass
capacitor is optional with some loss of sensitivity.
7
7
GND
-
Ground for RF analog blocks.
8
8
OSCin
I
Reference counter input. TCXO is connected via a coupling
capacitor.
-
9
-
N/C No connection.
9
10
GND
-
Ground for IF digital blocks.
10
11
foLD
O Multiplexed output of the RF/IF programmable counters, the
reference counters, the lock detect signals and the shift
registers. The output level is CMOS level. (see fout
Programmable Truth Table)
11
12
CLOCK
I
CMOS clock input. Serial data for the various counters is
transferred into the 22-bit shift register on the rising edge of
the clock signal.
-
13
-
N/C No connection.
12
14
DATA
I
Binary serial data input. The MSB of CMOS input data is
entered first. The control bits are on the last two bits. CMOS
input.
13
15
LE
I
Load enable CMOS input. When LE becomes high, the data
in the shift register is loaded into one of the four latches (by
the control bits).
14
16
GND
-
Ground for IF analog blocks.
6
Share Link: 