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S25FL064P

64-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Spansion Inc. 

S25FL064P

64-Mbit CMOS 3.0 Volt Flash Memory

with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Data Sheet

Distinctive Characteristics

Architectural Advantages

 Single power supply operation

– Full voltage range: 2.7 to 3.6V read and write operations

 Memory architecture

– Uniform 64 kB sectors

– Top or bottom parameter block (Two 64-kB sectors (top or

bottom) broken down into sixteen 4-kB sub-sectors each)

– 256-byte page size

– Backward compatible with the S25FL064A device

 Program

– Page Program (up to 256 bytes) in 1.5 ms (typical)

– Program operations are on a page by page basis

– Accelerated programming mode via 9V W#/ACC pin

– Quad Page Programming

 Erase

– Bulk erase function

– Sector erase (SE) command (D8h) for 64 kB sectors

– Sub-sector erase (P4E) command (20h) for 4 kB sectors

– Sub-sector erase (P8E) command (40h) for 8 kB sectors

 Cycling endurance

– 100,000 cycles per sector typical

 Data retention

– 20 years typical

 Device ID

– JEDEC standard two-byte electronic signature

– RES command one-byte electronic signature for backward

compatibility

 One time programmable (OTP) area for permanent, secure

identification; can be programmed and locked at the factory

or by the customer

 CFI (Common Flash Interface) compliant: allows host system

to identify and accommodate multiple flash devices

 Process technology

– Manufactured on 0.09 µm MirrorBit® process technology

 Package option

– Industry Standard Pinouts

– 16-pin SO package (300 mils)

– 8-contact WSON package (6 x 8 mm)

– 24-ball BGA package (6 x 8 mm), 5 x 5 pin configuration

– 24-ball BGA package (6 x 8 mm), 6 x 4 pin configuration

Performance Characteristics

 Speed

– Normal READ (Serial): 40 MHz clock rate

– FAST_READ (Serial): 104 MHz clock rate (maximum)

– DUAL I/O FAST_READ: 80 MHz clock rate or

20 MB/s effective data rate

– QUAD I/O FAST_READ: 80 MHz clock rate or

40 MB/s effective data rate

 Power saving standby mode

– Standby Mode 80 µA (typical)

– Deep Power-Down Mode 3 µA (typical)

Memory Protection Features

 Memory protection

– W#/ACC pin works in conjunction with Status Register Bits to

protect specified memory areas

– Status Register Block Protection bits (BP2, BP1, BP0) in status

register configure parts of memory as read-only

Software Features

– SPI Bus Compatible Serial Interface

Publication Number S25FL064P_00

Revision 08

Issue Date January 29, 2013

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