S3076TT 데이터 시트보기 (PDF) - Unspecified
부품명
상세내역
제조사
S3076TT Datasheet PDF : 18 Pages
| |||
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
S3076 FUNCTIONAL DESCRIPTION
The S3076 clock recovery device performs the clock
recovery function for SONET OC-48, Fibre Channel
(2125 Mbps), OC-24, Gigabit Ethernet, Fibre
Channel (1062.5 Mbps), OC-12 or OC-3 serial data
links with FEC capabilty up to 8 bytes per 255-byte
block. The chip extracts the clock from the serial data
inputs and provides retimed clock and data outputs.
A 155.52/19.44 MHz (156.25/19.53 MHz for Gigabit
Ethernet and 132.81/16.60 MHz for Fibre Channel)
reference clock is required for phase locked loop
start up and proper operation under loss of signal
conditions. An integral prescaler and phase locked
loop circuit is used to multiply this reference to the
nominal bit rate. The input data rate is selected by
the RATESEL inputs. (See Table 1.)
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by a value greater than
that stated in Table 7 with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 3.
Lock Detect
The S3076 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than that stated in
Table 7, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an attempt
to reacquire lock to data. If the recovered clock fre-
quency is determined to be within that stated in
Table 7, the PLL will be declared in lock and the lock
detect output will go active. The assertion of SDN will
also cause an out of lock condition.
Table 1. Data Rate Select
RATESEL0 RATESEL1
Operating Mode
REFCLK
Frequency
0
0
OC-3
155.52/19.44
0
1
OC-12
155.52/19.44
1
0
OC-24
155.52/19.44
1
1
OC-48
155.52/19.44
1
0
Gigabit Ethernet
156.25/19.53
1
0
Fibre Channel (1062.5 Mbps) 132.81/16.60
1
1
Fibre Channel (2125 Mbps) 132.81/16.60
Table 2. Reference Frequency Select
REFSEL
Reference Frequency for Data Rates with FEC Capability of X bytes per 255–Byte Block
(For OC-3/12/24/48 Rates Only)
X=0
X=3
X=4
X=5
X=6
X=7
X=8
0
19.44 MHz 19.99 MHz 20.15 MHz 20.31 MHz 20.48 MHz 20.65 MHz 20.83 MHz
1
155.52 MHz 159.91MHz 161.21 MHz 162.53 MHz 163.87 MHz 165.26 MHz 166.63 MHz
October 23, 2000 / Revision A
3
Share Link: 