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S3076TT Datasheet PDF : 18 Pages
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S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 5. Pin Assignment and Descriptions
Pin Name
Level I/O Pin#
Description
SERDATIP
SERDATIN
BYPASS
SDN
REFCLKP
REFCLKN
CAP1
CAP2
LCKREFN
RATESEL0
RATESEL1
TESTCLK
REFSEL
RST
TESTEN
SERDATOP
SERDATON
SERCLKOP
SERCLKON
LOCKDET
Diff.
CML
I
LVTTL
I
Single
Ended
I
LVPECL
Internally
Biased
Diff.
I
LVPECL
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
I
Diff.
CML
O
Diff.
CML
O
LVTTL O
3 Serial Data In. Clock is recovered from the transitions on these
2 inputs. Internally biased and terminated. (See Figure 10.)
46
Active High. Used to bypass the PLL. It allows transmission of data
input without clock recovery.
Signal Detect. Active Low. A single-ended 10K PECL input to be
driven by the external optical receiver module to indicate a loss of
45
received optical power. When SDN is inactive, the data on the Serial
Data In (SERDATIP/N) pins will be internally forced to a constant zero,
and the PLL will be forced to lock to the REFCLK inputs. When SDN
is active, data on the SERDATIP/N pins will be processed normally.
Reference Clock. 155.52/19.44 MHz (or equivalent Fibre Channel
6
7
or Gigabit Ethernet frequency) input used to establish the initial
operating frequency of the clock recovery PLL and also used as a
standby clock in the absence of data, during reset or when SDN is
inactive. Internally biased.
40 Loop Filter Capacitor. The external loop filter capacitor and resistors
39 are connected to these pins. (See Figure 14.)
17
Lock to Reference. Active Low. When active, the serial clock output
will be forced to lock to the local reference clock input [REFCLK].
20
19
Rate Select. Selects the operating mode (See Table 1.)
15
Test Clock. Test input signal used for production test. Connect to
Ground for normal operation. This input is internally pulled High.
18 Selects the reference frequency (See Table 2.)
16
Reset Input. Active High. Resets lock detect circuit and VCO divide-
by-N circuit for production test.
Test Enable. Active High. Bypasses the VCO for production test.
47 Connect to Ground for normal operation. This input is internally
pulled High.
28
27
Serial Data Out. This signal is the delayed version of the incoming
data stream (SERDATIP/N) updated on the falling edge of Serial
Clock Out (SERCLKOP/N).
34 Serial Clock Out. This signal is phase aligned with Serial Data Out
33 (SERDATO). (See Figure 8.)
Lock Detect. Clock recovery indicator. Set high when the internal
10 clock recovery has locked onto the incoming data stream.
LOCKDET is an asynchronous output.
6
October 23, 2000 / Revision A
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