I/O CIRCUIT SCHEMATICS
Input
VDD
30 -150 kΩ
VSS
Figure 1-4. I/O Circuit Type A
VDD
Data
Data
Disable(note)
Output
N-CH
VSS
NOTE: If data disable signal is active, halt mode,
the output becomes low state.
Figure 1-6. I/O Circuit Type C
S3C1840
VDD
Data
Data
Disable(note)
P-CH
Output
N-CH
VSS
NOTE: If data disable signal is active, halt mode,
the output becomes low state.
Figure 1-5. I/O Circuit Type B
VDD
Data
Output
N-CH
VSS
Figure 1-7. I/O Circuit Type D
1-5