S3C24A0 데이터 시트보기 (PDF) - Samsung

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S3C24A0

AN APPLICATION PROCESSOR FOR 2.5G/3G MOBILE PHONES

Samsung 

BSW rv0.1-0417-N01

S3C24A0 RISC MICROPROCESSOR

PRELIMINARY PRODUCT OVERVIEW

• 16-bit Watchdog Timer.

- Interrupt request or system reset at time-out.

• 4-ch DMA controller.

- Support memory to memory, IO to memory, memory to IO, and IO to IO

- Burst transfer mode to enhance the transfer rate.

• RTC (Real Time Clock)

- Full clock feature: msec, sec, min, hour, day, date, week, month, year.

- 32.768 KHz operation

- Alarm interrupt

- Time-tick interrupt

1.2.4 Serial Communication

• UART

- 2-channel UART with DMA-based or interrupt-based operation

- Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive

- Supports external clock for the UART operation (XuCLK)

- Programmable baud rate

- Supports IrDA 1.0

- Loop back mode for testing

- Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO

• IrDA

- Support IrDA 1.1 (1.152Mbps and 4Mbps)

- Support FIFO operation in the MIR and FIR mode

- Configurable FIFO Size (16-byte or 64-byte)

- Support Back-to-Back Transactions

- Support Software Selection Temic-IBM or HP Transceiver

- Support Little-endian access

• IIC-Bus Interface

- 1-ch Multi-Master IIC-Bus

- Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard

mode

• IIS-Bus Interface

- 1-ch IIS-bus for the audio-codec interface with DMA-based operation

- Serial, 8/16-bit per channel data transfers

- 128 Bytes (64-Byte + 64-Byte) FIFO for receive/transmit

- Supports IIS format and MSB-justified data format

1-5

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available.

Specifications and information herein are subject to change without notice.

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