S3C24A0A 데이터 시트보기 (PDF) - Samsung

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S3C24A0A

32-BIT RISC MICROPROCESSOR

Samsung 

Table of Contents (Continued)

Chapter 13 IIC-Bus Interface

Overview ....................................................................................................................................................... 13-1

The IIC-Bus Interface........................................................................................................................... 13-2

Start and Stop Conditions .................................................................................................................... 13-2

Data Transfer Format........................................................................................................................... 13-4

ACK Signal Transmission .................................................................................................................... 13-5

Read-Write Operation .......................................................................................................................... 13-6

Bus Arbitration Procedures .................................................................................................................. 13-6

Abort Conditions .................................................................................................................................. 13-6

Configuring the IIC-Bus........................................................................................................................ 13-6

Flowcharts of the Operations in Each Mode........................................................................................ 13-7

IIC-Bus Interface Special Registers.............................................................................................................. 13-11

Multi-Master IIC-Bus Control Register (IICCON)................................................................................. 13-11

Multi-Master IIC-Bus Control/Status Register (IICSTAT) .................................................................... 13-12

Multi-Master IIC-Bus Address Register (IICADD)................................................................................ 13-13

Multi-Master IIC-Bus Transmit/Receive Data Shift Register (IICDS) .................................................. 13-13

Multi-Master IIC-Bus Sdaout Delay Register (SDADLY) ..................................................................... 13-13

Chapter 14 IIS-Bus Interface

Overview ....................................................................................................................................................... 14-1

Features ............................................................................................................................................... 14-1

Block Diagram...................................................................................................................................... 14-1

Functional Descriptions........................................................................................................................ 14-2

Transmit or Receive Only Mode .......................................................................................................... 14-2

Dma Transfer ....................................................................................................................................... 14-2

Transmit and Receive Mode ................................................................................................................ 14-2

Audio Serial Interface Format....................................................................................................................... 14-3

IIS-Bus Format ..................................................................................................................................... 14-3

MSB(Left) Justified............................................................................................................................... 14-3

Sampling Frequency and Master Clock............................................................................................... 14-4

IIS-Bus Interface Special Registers.............................................................................................................. 14-5

IIS Control Register (IISCON).............................................................................................................. 14-5

IIS Mode Register (IISMOD) ................................................................................................................ 14-6

IIS Prescaler Register (IISPSR)........................................................................................................... 14-7

IIS FIFO Control Register (IISFCON) .................................................................................................. 14-7

IIS FIFO Register (IISFIFO) ................................................................................................................. 14-8

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S3C24A0A MICROPROCESSOR

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