S3C72H8 데이터 시트보기 (PDF) - Samsung

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S3C72H8

The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsung's state-of-the-art 4-bit product development approach, SAM47

Samsung 

PRODUCT OVERVIEW

S3C72H8/P72H8

FEATURES

Architecture

– SAM47 4-bit CPU core

Memory

– Data Memory: 512 × 4 bits

– Program Memory: 8196 × 8 bits

(Including LCD display RAM)

Memory-Mapped I/O Structure

– Data memory bank 15

Interrupts

– Three internal vectored interrupts

– Three external vectored interrupts

– Two quasi-interrupts

8-Bit Timer/Counter (T0)

– Programmable 8-bit timer

– External event counter

– Arbitrary clock frequency output

– External clock signal divider

16-Bit Frequency Counter (FC)

– a 16-bit binary up-counter

– External event counter

– Gate function control

Watch-Dog TIMER and Basic Timer

– 8-bit counter + 3-bit counter

– Overflow signal of 8-bit counter makes a basic

timer interrupt. And control the oscillation warm-

up time

– Overflow signal of 3-bit counter makes a system

reset

Watch Timer

– Real-time and interval time measurement

– Four frequency outputs to buzzer sound

– Clock source generation for LCD

LCD Controller/Driver

– 26 segment and 4 common terminals

– Maximum 13-digit LCD direct drive capability

– Display modes: Static, 1/2, 1/3, 1/4 duty

– Voltage regulator and booster (1/3 bias: 1, 2, or

3V, 1/2 bias: 1.5, 3V)

Analog Comparator

– 2 Ch Comparator (Each CnP, CnN, CnOUT pins)

Bit Sequential Carrier

– Support 16-bit serial data transfer in arbitrary

format

I/O Ports

– 21 pins for standard I/O

– 26 pins for LCD segment output

– 4 pins for LCD common output

– Two input pins for external interrupts

Oscillation Sources

– Crystal, ceramic, or RC for main system clock

– Crystal or external oscillator for subsystem clock

– Main system clock frequency: 4.19 MHz (typical)

– Subsystem clock frequency: 32.768 kHz

– CPU clock divider circuit (by 4, 8, or 64 main, and

by 4 for sub clock)

Power Down Mode

– Idle mode (only CPU clock stops)

– Stop mode (main or sub-system oscillation stops)

Voltage Level Detector

– VDD level detection circuit (2.2, 2.4, 3, or 4.0V)

– External pin level detect mode

Operating Voltage Range

– 1.8V to 5.5V at 3 MHz

– 2.0V to 5.5V at 4.19 MHz

Package Type

– 64-pin QFP

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