S3C72H8 데이터 시트보기 (PDF) - Samsung

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S3C72H8

The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsung's state-of-the-art 4-bit product development approach, SAM47

Samsung 

PRODUCT OVERVIEW

S3C72H8/P72H8

Table 1-1. S3C72H8 Pin Descriptions (Continued)

Pin Name

KS0-KS3

ExtRef

TCL0

FCL

TCLO0

COM0-COM3

SEG0-SEG25

CA, CB

VLC0-VLC2

C0P, C0N,

C0OUT

C1P, C1N,

C1OUT

RESET

VDD

VSS

TEST

SDAT

SCLK

VPP

Pin

Type

I/O

I/O

I/O

I/O

I/O

O

O

–

–

I/O

I/O

I

–

–

–

–

I/O

I/O

–

Description

Quasi-interrupt input with falling edge detection

External Reference input

External clock input for timer/counter 0

External clock input for frequency counter

Timer/counter 0 clock output

LCD common signal output

LCD segment output

Voltage booster capacitor pins

Voltage booster output pins (VLC0 is the regulated

output, VLC1 is the 2* VLC0 output, VLC2 is the 3* VLC0

output)

Comparator 0 non-inverting input, inverting input and

output. C0Out can be configured as C-MOS push-pull

or N-Ch open drain output

Comparator 1 non-inverting input, inverting input and

output. C1Out can be configured as C-MOS push-pull

or N-Ch open drain output

Reset signal for chip initialization

Main power supply

Ground

Test signal input (must be connected to VSS)

Serial data for OTP programming

Serial clock for OTP programming

Power supply pin for EPROM cell writing

Number

(64-QFP)

25-28

6

19

20

21

61-64

35-60

1, 2

3-5

29-31

32-34

16

9

10

13

7

8

13

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Pin

P6.0-P6.3

P0.0

P2.2

P2.3

P3.0

–

–

–

–

Circuit

Type

D-1

D-1

D-1

D-1

D-1

H-16

H-16

–

–

P4.0-P4.2 –

P4.3-P5.1 –

–

B

–

–

–

–

VPP

–

P0.1

P0.2

TEST

NOTE: Pull-up resistors for ports 0, 2, 3, and 6 are automatically disabled if they are configured to output mode.

But pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode.

1-6

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