S3C72N4 데이터 시트보기 (PDF) - Samsung

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S3C72N4

The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47

Samsung 

S3C72N2/C72N4/P72N4

BLOCK DIAGRAM

PRODUCT OVERVIEW

Watchdog

Timer

Basic

Timer

INT0, INT1, INT2

Xin Xout

RESET XTin XTout

Watch

Timer

P2.3/BUZ

P1.3/TCL0

P2.0/TCLO0

8-Bit Timer/

Counter0

P6.0-P6.3/

KS0-KS3

I/O Port 6

P8.0-P8.7

SEG24-SEG31

Output Port 8

Interrupt

Control

Block

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic

and

Logic Unit

Instruction

Register

Program

Counter

Program

Status

Word

Stack

Pointer

288 x 4-Bit

Data Memory

2/4 KByte

Program

Memory

LCD

Driver/

Controller

Input

Port 1

I/O Port 2

I/O Port 3

BIAS

VLC0-VLC2

LCDCK/P3.0

LCDSY/P3.1

COM0-COM3

SEG0-SEG23

P8.0-P8.7/

SEG24-SEG31

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/TCL0

P2.0/TCLO0

P2.1

P2.2/CLO

P2.3/BUZ

P3.0/LCDCK

P3.1/LCDSY

P3.2

P3.3

Figure 1-1. S3C72N2/C72N4 Simplified Block Diagram

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