SY100E122(1998) 데이터 시트보기 (PDF) - Micrel
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SY100E122 Datasheet PDF : 4 Pages
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9-BIT
BUFFER
SY10E122
SY100E122
FEATURES
s 500ps max. propagation delay
s Extended 100E VEE range of –4.2V to –5.5V
s Fully compatible with industry standard 10KH,
100K I/O levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E122
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E122 are 9-bit buffers designed for use in
new, high-performance ECL systems. The E122 provides
nine non-inverting buffers.
BLOCK DIAGRAM
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
D8
Q8
PIN CONFIGURATION
D7
D6
D5
VEE
D4
D3
D2
25 24 23 22 21 20 19
26
18
27
17
28
PLCC
16
1
TOP VIEW
15
J28-1
2
14
3
13
4
12
5 6 7 8 9 10 11
Q7
Q6
VCC
Q5
Q4
VCCO
Q3
PIN NAMES
Pin
D0-D8
Q0-Q8
VCCO
Function
Data Inputs
Data Outputs
VCC to Output
Rev.: D Amendment: /2
1
Issue Date: May, 1998
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