SAA5233 데이터 시트보기 (PDF) - Philips Electronics

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SAA5233

Dual standard PDC decoder

Philips Electronics 

Philips Semiconductors

Dual standard PDC decoder

BLOCK DIAGRAM

Objective specification

SAA5233

handbook, full pagewidth

14

AD

SCL

SDA

12

13

I2C BUS

INTERFACE

MEMORY

INTERFACE

AND RAM

15

INT

INTERRUPT

CONTROL

SAA5233

VDD

VSS1

VSS2

VSS3

VSS4

VSS5

4

TELETEXT

AND VPS

5

CONTROL

9

10

11

16

DATA SLICER

AND CLOCK

REGENERATOR

POWER

ON RESET

13.5 MHz

27 MHz

1.125 MHz

27 MHz

OSCILLATOR

AND DIVIDER

ANALOGUE

TO DIGITAL

CONVERTER

678

OSCOUT OSCIN OSCGND

8/30/2

ACQUISITION

AND

DECODING

VPS

ACQUISITION

AND

DECODING

PLL AND

TIMING

INPUT

CLAMP

AND SYNC

SEPARATOR

123

MLB725

CVBS BLACK IREF

June 1994

Fig.1 Block diagram; pin numbers for DIP16.

3

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