SAA5250P 데이터 시트보기 (PDF) - Philips Electronics

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SAA5250P

Interface for data acquisition and control (for multi-standard teletext systems)

Philips Electronics 

Philips Semiconductors

Interface for data acquisition and control

(for multi-standard teletext systems)

Product specification

SAA5250

R3 register

Table 7 R3 register contents

R35 TO R30

6-BIT FORMAT MAXIMUM/DEFAULT VALUE

000000 = 0

000001 = 1

−

−

−

111111 = 63

This 6-bit byte gives:

• In the DIDON long and short mode, a maximum format in case of corrupted transmission (multiple errors on the

Hamming corrector)

• A possible 63-bit format for all types of prefix

R4 register

Table 8 R4 register contents

R47 TO R40

8-bit register used for storing the framing code value which will be compared with the third byte of each data

line

R5 register

Table 9 R5 register contents

R57

NEGATIVE/POSITIVE

0 = negative edge for sync signal

1 = positive edge for sync signal

R56 TO R50

SYNCHRONIZATION DELAY

7-bit sync delay, giving a maximum

delay of (27 − 1) × 106 µs/F (Hz)

Note

1. F = data clock acquisition frequency (DCK).

Using R57 it is possible to start the internal synchronization delay (tDVAL) on the positive or negative edge.

R6 write command register

This is a fictitious register. Only the address code (see Table 2) is required to reset the CIDAC. See Table 11 for the

status of the FIFO memory on receipt of this command.

R7 register

Table 10 R7 register contents

R75 TO R70

6-bit register used to give a maximum colour burst blanking signal of: (26 − 1) × 106 µs/F (Hz)

Note

1. F = data clock acquisition frequency.

January 1987

10

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