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SAA5252

Line twenty-one acquisition and display (LITOD)

Philips Electronics 

Philips Semiconductors

Line twenty-one acquisition and display (LITOD)

Product specification

SAA5252

DISPLAY GENERATOR

General description

The displayed characters are defined on a 5-by-12 matrix

within a 7-by-13 window, allowing one blank pixel either

side of the character and a blank pixel row above. There

are a number of display options available controlled by

Register 1, or external pins in ‘stand-alone’ mode.

The three display modes are video, text and caption, the

device is powered up in the video mode.

The display generator reads the Pre-amble Address Code

(PAC) then the data associated with that row. Each

character is then rounded after which it can be italicized

and/or underlined, depending on the PAC or mid-row

codes, before being passed on to the output circuitry.

Figure 6 shows the character set.

Display of external On-Screen Display (OSD) facilities

The R, G, B and BLAN outputs of the display have the

capability to be put in a 3-state mode allowing other OSD

devices to take control of the television R, G, B and BLAN

signals.

When the BLANIN is held HIGH then the R, G, B and

BLAN outputs from display are disabled and the R, G, B

and BLAN signals come directly from the RGBIN and

BLANIN inputs. This will allow On-Screen Display to be

placed on top of the captioning without any corruption,

leaving the captions intact when the On-Screen Display is

switched off (BLANIN goes LOW). In this form of operation

the RGBIN and RGBOUT pins can be considered

transparent; BLANIN goes through the normal output

buffer to BLAN.

Table 1 Register map (WRITE)

REGISTER

D7

00

DF1/2

01

CLEAR

02

−

03

−

04

−

D6

D5

D4

RGB, BLAN H

+ve/−ve

+ve/−ve

V

+ve/−ve

CH 2/1

NARROW/ ACQ OFF

WIDE

−

−

−

−

−

COL4

OSD6

OSD5

OSD4

D3

H3

EN1

ROW3

COL3

OSD3

Table 2 Register map (READ)

REGISTER

D7

80

POR

D6

0

D5

0

D4

0

D3

F1/F2

81

PARITY DATA

ERROR BIT 7

82

PARITY DATA

ERROR BIT 7

DATA

BIT 6

DATA

BIT 6

DATA

BIT 5

DATA

BIT 5

DATA

BIT 4

DATA

BIT 4

D2

H2

EN0

ROW2

COL2

OSD2

D2

EDS

DATA

BIT 3

DATA

BIT 3

D1

H1

M1

ROW1

COL1

OSD1

D0

H0

M0

ROW0

COL0

OSD0

D1

PARITY

SHUTDOWN

DATA

BIT 2

DATA

BIT 2

D0

DATA

READY

DATA

BIT 1

DATA

BIT 1

1996 Jul 18

11

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