C161S 데이터 시트보기 (PDF) - Infineon Technologies

부품명

상세내역

제조사

C161S

16-Bit Single-Chip Microcontroller

Infineon Technologies 

C161S

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

RD

25

O

External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR/

26

O

External Memory Write Strobe. In WR-mode this pin is

WRL

activated for every external data write access. In WRL-mode

this pin is activated for low byte data write accesses on a

16-bit bus, and for every data write access on an 8-bit bus.

See WRCFG in register SYSCON for mode selection.

ALE

27

O

Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the

multiplexed bus modes.

EA

28

I

External Access Enable pin. A low level at this pin during and

after Reset forces the C161S to begin instruction execution

out of external memory. A high level forces execution out of

the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

PORT0

IO

P0L.0-7 29-36

P0H.0-7 39-46

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state.

In case of an external bus configuration, PORT0 serves as

the address (A) and address/data (AD) bus in multiplexed

bus modes and as the data (D) bus in demultiplexed bus

modes.

Demultiplexed bus modes:

Data Path Width: 8-bit

16-bit

P0L.0 – P0L.7:

D0 – D7

D0 – D7

P0H.0 – P0H.7: I/O

D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit

16-bit

P0L.0 – P0L.7:

AD0 – AD7 AD0 – AD7

P0H.0 – P0H.7: A8 – A15 AD8 – AD15

Data Sheet

6

V1.0, 2003-11

Share Link: