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SAA6581

RDS/RBDS demodulator

NXP Semiconductors. 

Philips Semiconductors

RDS/RBDS demodulator

Product specification

SAA6581

FUNCTIONAL DESCRIPTION

RDS/RBDS signal demodulation

BANDPASS FILTER

The bandpass filter has a centre frequency of 57 kHz. It

selects the RDS/RBDS sub-band from the multiplex signal

MPX and suppresses the audio signal components. The

filter block contains an analog anti-aliasing filter at the

input followed by an 8th order switched capacitor

bandpass filter and a reconstruction filter at the output.

CLOCKED COMPARATOR

The comparator digitizes the output signal from the 57 kHz

bandpass filter for further processing by the digital

RDS/RBDS demodulator. To attain high sensitivity and to

avoid phase distortion, the comparator input stage has

automatic offset compensation.

DEMODULATOR

The demodulator provides all functions of the SAA6579

and improves performance under weak signal conditions.

Demodulator functions include:

• 57 kHz carrier regeneration from the two sidebands

(Costas loop)

• Symbol integration over one RDS clock period

• Bi-phase symbol decoding

• Differential decoding

• Synchronization of RDS/RBDS output data.

The RDS/RBDS demodulator recovers and regenerates

the continuously transmitted RDS/RBDS data stream in

the MPX signal and provides clock RDCL for the output

signals and data output RDDA for further processing by an

RDS/RBDS decoder, for example CCR921 or CCR922.

ARI CLAMP

The demodulator checks the input signal for presence of

RDS only, or RDS plus ARI transmissions. After a fixed

test period, if the SYNC input is set HIGH the demodulator

locks in the ‘verified’ condition (see Table 1). If SYNC is set

LOW, the ARI clamping is reset (disabled). After SYNC

returns to HIGH, the demodulator resumes checking the

input signal.

Table 1 Control pin SYNC

SYNC

LOW

HIGH

ARI CLAMPING

internal ARI clamping disabled

ARI clamping allowed to be logged

SIGNAL QUALITY DETECTION

Output QUAL indicates the safety of the regenerated RDS

data (HIGH = ‘good’ data; LOW = ‘unsafe’ data).

Oscillator and system clock generator

For good performance of the bandpass and demodulator

stages, the demodulator requires a crystal oscillator with a

frequency of 4.332 or 8.664 MHz. The demodulator can

operate with either frequency (see Table 2), so that a radio

set with a microcontroller can run, in this case, with one

crystal only. The demodulator oscillator can drive the

microcontroller, or vice versa.

Table 2 Control pins TCON and MODE

TCON

HIGH

HIGH

MODE

LOW

HIGH

OSCILLATOR FREQUENCY

4.332 MHz

8.664 MHz

The clock generator generates the internal 4.332 MHz

system clock and timing signal derivatives.

Power supply and internal reset

The demodulator has separate power supply inputs for the

digital and analog parts of the device. For the analog

functions an additional reference voltage (1⁄2VDDA) is

internally generated and available via the output pin Vref.

The demodulator requires a defined reset condition. The

demodulator generates automatically a reset signal after

the power supply VDDA is switched on, or at a voltage-drop.

2003 Oct 10

5

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