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C164CI 데이터 시트보기 (PDF) - Infineon Technologies

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C164CI
Infineon
Infineon Technologies Infineon
C164CI Datasheet PDF : 79 Pages
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C164CI/SI
C164CL/SL
Table 2
Pin Definitions and Functions (contd)
Symbol Pin
No.
Input Function
Outp.
P4
IO
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 4 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 4 is
selectable (TTL or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:1)
P4.0 17
O
A16
Least Significant Segment Address Line,
O
CS3
Chip Select 3 Output
P4.1 18
O
A17
Segment Address Line,
O
CS2
Chip Select 2 Output
P4.2 19
O
A18
Segment Address Line,
O
CS1
Chip Select 1 Output
P4.3 22
O
A19
Segment Address Line,
O
CS0
Chip Select 0 Output
P4.5 23
O
A20
Segment Address Line,
I
CAN1_RxD CAN 1 Receive Data Input
P4.6 24
O
A21
Most Significant Segment Address Line,
O
CAN1_TxD CAN 1 Transmit Data Output
RD
25
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/ 26
O
WRL
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
ALE 27
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
Data Sheet
6
V2.0, 2001-05

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