SC26C562(2006) 데이터 시트보기 (PDF) - Philips Electronics
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SC26C562 Datasheet PDF : 22 Pages
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Philips Semiconductors
CMOS dual universal serial communications controller
(CDUSCC)
Product data sheet
SC26C562
PIN CONFIGURATION
INDEX
CORNER
7
8
1
47
46
PLCC
20
21
TOP VIEW
34
33
Pin Function
Pin Function
1 IACKN
2 A3
3 A2
4 A1
5 RTxDAKBN/GPI1BN
6 IRQN
7 NC
8 RDYN
9 RTSBN/SYNOUTBN
10 TRxCB
11 RTxCB
12 DCDBN/SYNIBN
13 NC
14 RxDB
15 TxDB
16 TxDAKBN/GPI2BN
17 RTxDRQBN/GPO1BN
18 TxDRQBN/GPO2BN/RTSBN
19 CTSBN/LCBN
20 D7
21 D6
22 D5
23 D4
24 RDN
25 RESETN
26 GND
27 CSN
28 WRN
29 EOPN
30 D3
31 D2
32 D1
33 D0
34 NC
35 CTSAN/LCAN
36 TxDRQAN/GPO2AN/RTSAN
37 RTxDRQAN/GPO1AN
38 TxDAKAN/GPI2AN
39 TxDA
40 RxDA
41 NC
42 DCDAN/SYNIAN
43 RTxCA
44 TRxCA
45 RTSAN/SYNOUTAN
46 X2
47 X1/CLK
48 RTxDAKAN/GPI1AN
49 A6
50 A5
51 A4
52 VCC
SD00740
Figure 2. Pin configuration
PIN DESCRIPTION
MNEMONIC
PIN
A1–A6
4-2,
51-49
D0–D7
33-30,
23-20
RDN
24
WRN
28
CSN
27
RDYN
8
TYPE
I
I/O
I
I
I
O
NAME AND FUNCTION
Address Lines: Active-HIGH. Address inputs which specify which of the internal registers is
accessed for read/write operation.
Bidirectional Data Bus: Active-HIGH, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data,
command and status transfers between the CPU and the CDUSCC take place over this bus. The
data bus is enabled when CSN and RDN, or CSN and WRRN are LOW during interrupt
acknowledge cycles and single address DMA acknowledge cycles.
Read Strobe: Active-LOW input. When active and CSN is also active, causes the content of the
addressed register to be present on the data bus. RDN is ignored unless CSN is active.
Write Strobe: Active-LOW input. When active and CSN is also active, the content of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of WRN. WRN is ignored
unless CEN is active.
Chip Select: Active-LOW input. When active, data transfers between the CPU and the CDUSCC are
enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When CSN is HIGH, the data
lines are placed in the 3-State condition (except during interrupt acknowledge cycles and single
address DMA transfers).
Ready: Active-LOW, open drain. Used to synchronize data transfers between the CPU and the
CDUSCC. It is valid only during read and write cycles where the CDUSCC is configured in ‘wait on
Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always inactive. RDYN becomes active
on the leading edge of RDN and WRN if the requested operation cannot be performed (viz, no data
in RxFIFO in the case of a read or no room in the TxFIFO in the case of a write).
2006 Aug 10
5
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