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SG3526BDW

REGULATING PULSE WIDTH MODULATOR

Microsemi Corporation 

SG1526B/SG2526B/SG3526B

APPLICATION INFORMATION (continued)

DIGITAL CONTROL PORTS

The three digital control ports of the SG1526B are bi-

directional. Each pin can drive TTL and 5 volt CMOS logic

directly, up to a fan-out of 10 low-power Schottky gates.

Each pin can also be directly driven by open-collector TTL,

open-drain CMOS, and open-collector voltage comparators,

fan-in is equivalent to 1 low-power Schottky gate. Each port

is normally HIGH; the pin is pulled LOW to activate the

particular function. Driving SYNC LOW initiates a discharge

cycle in the oscillator. Pulling SHUTDOWN LOW immedi-

ately inhibits all PWM output pulses. Holding RESET LOW

discharges the soft-start capacitor. The logic threshold is

+1.1 volts at +25oC. Noise immunity can be gained at the

expense of fan-out with an external 2K pull-up resistor to +5

volts.

FIGURE 23

DIGITAL CONTROL PORT SCHEMATIC

OSCILLATOR

The oscillator is programmed for frequency and dead time

with three components: RT CT, and RD. Two waveforms are

generated: a sawtooth waveform at pin 10 for pulse width

modulation, and a logic clock at pin 12. The following

procedure is recommended for choosing timing values:

1. With RD = 0Ω (pin 11 shorted to ground) select values

for RT and CT from Figure 19 to give the desired

oscillator period. Remember that the frequency at

each driver output is half the oscillator frequency, and

the frequency at the +VC terminal is the same as the

oscillator frequency.

2. If more dead time is required, select a larger value of

RD using Figure 14 as a guide. At 40 KHz dead time

increases by 300 ns/Ω.

3. Increasing the dead time will cause the oscillator

frequency to decrease slightly. Go back and de-

crease the value of RT slightly to bring the frequency

back to the nominal design value.

The SG1526B can be synchronized to an external logic clock

by programming the oscillator to free-run at a frequency 10%

slower than the sync frequency. A periodic LOW logic pulse

approximately 0.5 µSec wide at the SYNC pin will then lock

the oscillator to the external frequency.

Multiple devices can be synchronized together by program-

ming one master unit for the desired frequency, and then

sharing its sawtooth and clock waveforms with the slave

units. All CT terminals are connected to the CT pin of the

master, and all SYNC terminals are likewise connected to

the SYNC pin of the master. Slave RT terminals should not

be left open; at least 50K should be connected from each pin

to ground. Slave R terminals may be either left open or

D

grounded.

FIGURE 24.

OSCILLATOR CONNECTIONS ANDD WAVEFORMS

ERROR AMPLIFIER

The error amplifier is a transconductance design, with an

output impedance of 2 megohms. Since all voltage gain

takes place at the output pin, the open-loop gain/frequency

characteristics can be controlled with shunt reactance to

ground. When compensated for unity-gain stability with 100

pF, the amplifier has an open-loop pole at 400 Hz.

The input connections to the error amplifier and determined

by the polarity of the switching supply output voltage. For

positive supplies, the common-mode voltage is +5.0 volts

and the feedback connections in Figure 25A are used. With

negative supplies, the common-mode voltage is ground and

(A)

(B)

the feedback divider is connected between the negative

output and the +5.0 volt reference voltage, as shown in

Figure 25B.

FIGURE 25.

ERROR AMPLIFIER CONNECTIONS

Rev 1.1a

Copyright © 1994

11861 Western Avenue ∞ Garden Grove, CA 92841

7

(714) 898-8121 ∞ FAX: (714) 893-2570

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