STA020 데이터 시트보기 (PDF) - STMicroelectronics
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STA020 Datasheet PDF : 12 Pages
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STA020
GENERAL DESCRIPTION
The STA020 is a monolithic CMOS circuit that en-
codes and transmits audio and digital data ac-
cording to the AES/EBU, IEC 958, S/PDIF, and
EIAJ CP-340 interface standards. The chip ac-
cepts audio and control data separately; multiplex
and biphase-mark encode the data internally and
drive it, directly or through a transformer, to a
transmission line.
The STA020 has dedicated pins for the most im-
portant control bits and a serial input port for the
C, U and V bits.
Line Drivers
The differential line drivers for STA020 are low
skew, low impedance, differential outputs capable
of driving 110Ohm transmission lines. (RS422
line driver compatible).
They can also be disabled by resetting the device
(RST = low).
STA020 DESCRIPTION
The STA020 accepts 16 to 24-bit audio samples
through a serial port configured in one of seven
formats; provides several pins dedicated to par-
ticular channel status bits and allows all channel
status, user and validity bits to be serially input
through port pins. This data is multiplexed, the
parity bit is generated and the bit stream is
biphase-mark encoded and driven through an
RS422 line driver.
The STA020 operates as a professional or con-
sumer interface transmitter selectable by pin 2,
PRO. As a professional interface device, the
dedicated channel status input pins are defined
according to the professional standard, and the
CRC code (C.S. byte 23) can be internally gener-
ated.
As a consumer device, the dedicated channel
status input pins are defined according to the
consumer standard. A submode provided under
the consumer mode is compact disk, CD, mode.
When transmitting data from a compact disk, the
CD subcode port can accept CD subcode data,
extract channel status information from it, and
transmit it as user data.
The master clock , MCK, controls timing for the
entire chip and must be 128xFs. As an example,
if stereo data is input to the STA020 at 44.1kHz,
MCK input must be 128 times that or 5.6448MHz.
Audio Serial Port
The audio serial port is used to enter audio data
and consists of three pins: SCK, SDATA and
FSYNC, SCK clocks in SDATA, which is double
buffered, while FSYNC delineates the audio sam-
ples and may indicate the particular channel, left
or right. To support many different interfaces, M2,
M1 and M0 select one of seven different formats
for the serial port. The coding is shown in Table 3
while the formats are shown in Figure 3.
Format 0 and 1 are designed to interface with
Crystal ADCs. Format 2 communicates with Mo-
torola and TI DSPs. Format 3 is reserved. Format
4 is compatible with the I2S standard. Formats 5
and 6 make the STA020 look similar to existing
16- and 18-bit DACs and interpolation filters. For-
mat 7 is an MSB-last format and is conducive to
serial arithmetic. SCK and FSYNC are outputs in
Format 0 and inputs in all other formats. In For-
mat 2, the rising edge of FSYNC delineates sam-
ples and the falling edge must occur a minimum
of one bit period before or after the rising edge.
In all formats except 2, FSYNC contains left/right
information requiring both edges of FSYNC to de-
lineate samples. Formats 5 and 6 require a mini-
mum of 16- or 18-bit audio words respectively. In
all formats other than 5 and 6, the STA020 can
accept any word length from 16 to 24 bits by add-
ing leading zeros in format 7 and trailing zeros in
the other formats, or by restricting the number of
SCK periods between active edges of FSYNC to
the sample word length.
FSYNC must be derived from MCK, either
through a DSP using the same clock or using
counters. If SFYNC moves (jitters) with respect to
MCK by four MCK periods, the internal counters
and CBL may be reset.
Table 1. Audio Port Modes
M2 M1 M0
Format
0 0 0 0 - FSYNC & SCK Output
0 0 1 1 - Left/Right, 16-24 Bits
0 1 0 2 - Word Sync, 16-24 Bits
0 1 1 3 - Reserved
1
0
0 4 - Left/Right, I2S Compatible
1 0 1 5 - LSB Justified, 16 Bits
1 1 0 6 - LSB Justified, 18 Bits
1 1 1 7 - MSB Last, 16-24 Bits
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