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SI4112G

DUAL-BAND RF S YNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS

Silicon Laboratories 

Si4133G

Table 6. Si4133G-BT VCO Characteristics

VCO Fcen Range Cnom Lpkg Lext Range

(MHz)

(pF) (nH)

(nH)

Min Max

Min Max

RF1 947 1720 4.3 2.0 0.0 4.6

RF2 789 1429 4.8 2.3 0.3 6.2

IF 526 952 6.5 2.1 2.2 12.0

in addition to 2.3 nH of LPKG (Si4133G-BT), will present

the correct total inductance to the VCO. In

manufacturing, the external inductance can vary ±10%

of its nominal value and the Si4133G will correct for the

variation with the self-tuning algorithm.

In most cases, particularly for the RF VCOs, the

requisite value of the external inductance is small

enough to allow a PC board trace to be utilized. During

initial board layout, a length of trace approximating the

desired inductance can be used. For more information,

please refer to Application Note 31.

Table 7. Si4133G-BM VCO Characteristics

VCO Fcen Range Cnom Lpkg Lext Range

(MHz)

(pF) (nH)

(nH)

Min Max

Min Max

RF1 947 1720 4.3 1.5 0.5 5.1

RF2 789 1429 4.8 1.5 1.1 7.0

IF 526 952 6.5 1.6 2.7 12.5

Self-Tuning Algorithm

The self-tuning algorithm is initiated immediately

following power-up of a PLL or, if the PLL is already

powered, following a change in its programmed output

frequency. This algorithm attempts to tune the VCO so

that its free-running frequency is near the desired output

frequency. In so doing, the algorithm will compensate

for manufacturing tolerance errors in the value of the

external inductance connected to the VCO. It will also

reduce the frequency error for which the PLL must

correct to get the precise desired output frequency. The

self-tuning algorithm will leave the VCO oscillating at a

frequency in error by somewhat less than 1% of the

desired output frequency.

L PKG

2

L E XT

L PKG

2

Figure 15. External Inductance Connection

After self-tuning, the PLL controls the VCO oscillation

frequency. The PLL will complete frequency locking,

eliminating any remaining frequency error. Thereafter, it

will maintain frequency-lock, compensating for effects

caused by temperature and supply voltage variations.

The Si4133G’s self-tuning algorithm will compensate for

component value errors at any temperature within the

specified temperature range. However, the ability of the

PLL to compensate for drift in component values that

occur after self-tuning is limited. For external

inductances with temperature coefficients around

±150 ppm/oC, the PLL will be able to maintain lock for

changes in temperature of approximately ±30oC.

As a design example, suppose it is desired to

synthesize frequencies in a 25 MHz band between

1120 MHz and 1145 MHz. The center frequency should

be defined as midway between the two extremes, or

1132.5 MHz. The PLL will be able to adjust the VCO

output frequency ±5% of the center frequency, or

±56.6 MHz of 1132.5 MHz (i.e., from approximately

1076 MHz to 1189 MHz, more than enough for this

example). The RF2 VCO has a CNOM of 4.8 pF, and a

4.1 nH inductance (correct to two digits) in parallel with

this capacitance will yield the desired center frequency.

An external inductance of 1.8 nH should be connected

between RFLC and RFLD as shown in Figure 15. This,

Applications where the PLL is regularly powered down

(such as GSM) or switched between channels minimize

or eliminate the potential effects of temperature drift

because the VCO is re-tuned when it is powered up or

when a new frequency is programmed. In applications

where the ambient temperature can drift substantially

after self-tuning, it may be necessary to monitor the

LDETB (lock-detect bar) signal on the AUXOUT pin to

determine the locking state of the PLL. (See "Auxiliary

Output (AUXOUT)" on page 18 for how to select

LDETB.)

The LDETB signal is normally low after self-tuning is

completed but will rise to a logic high condition when

16

Rev. 1.1

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