SI4112G 데이터 시트보기 (PDF) - Silicon Laboratories

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SI4112G

DUAL-BAND RF S YNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS

Silicon Laboratories 

Si4133G

Register 0. Main Configuration Address Field = A[3:0] = 0000

Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name 0 0 0 0 AUXSEL 0 0 0 0 0 0 LPWR 0 AUTO 0 1 0

[1:0]

PDB

Bit

17:14

13:12

11:6

5

4

3

2

1

0

Name

Reserved

AUXSEL

[1:0]

Reserved

LPWR

Reserved

AUTOPDB

Reserved

Reserved

Reserved

Function

Program to zero.

Auxiliary Output Pin Definition.

00 = Reserved.

01 = Force output low.

10 = Reserved.

11 = Lock Detect—LDETB.

Program to zero.

Output Power-Level Settings for IF Synthesizer Circuit.

0 = RLOAD < 500 Ω—normal power mode.

1 = RLOAD ≥ 500 Ω—low power mode.

Program to zero.

Auto Power Down

0 = Software powerdown is controlled by Register 2.

1 = Equivalent to setting all bits in Register 2 = 1.

Program to zero.

Program to one.

Program to zero.

Rev. 1.1

21

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