SI5338G 데이터 시트보기 (PDF) - Silicon Laboratories
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SI5338G Datasheet PDF : 170 Pages
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Si5338
Table 6. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Input Impedance
RIN
10
—
—
Input Capacitance
CIN
—
3.5
—
Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)
Frequency
fIN
Input Voltage
VI
Input Voltage Swing
CMOS
200 MHz
5
—
200
–0.1
—
3.63
0.8
—
VDD+10%
Rise/Fall Time
Duty Cycle2,3
tR/tF
20%–80%
DC
< 4 ns tr/tf
—
—
2
40
—
60
Input Capacitance
CIN
Output Clocks (Differential)
—
2.0
—
0.16
—
350
Frequency4
LVPECL, LVDS
367
fOUT
550
—
473.33
—
710
HCSL
0.16
—
250
LVPECL Output Voltage
VOC
VSEPP
common mode
peak-to-peak single-
ended swing
—
0.55
VDDO–1.45 V
0.8
—
0.96
LVDS Output Voltage
(2.5/3.3 V)
VOC
VSEPP
common mode
peak-to-peak single-
ended swing
1.125
0.25
1.2
0.35
1.275
0.45
VOC
common mode
0.8
LVDS Output Voltage
(1.8 V)
VSEPP
peak-to-peak single-
ended swing
0.25
0.875
0.35
0.95
0.45
HCSL Output Voltage
VOC
VSEPP
common mode
peak-to-peak single-
ended swing
0.35
0.575
0.375
0.725
0.400
0.85
Rise/Fall Time
Duty Cycle2
tR/tF
20%–80%
DC
—
—
450
45
—
55
Notes:
1. For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns
2. Not in PLL bypass mode.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns
4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6.
5. Includes effect of internal series 22 resistor.
Units
k
pF
MHz
V
Vpp
ns
%
pF
MHz
MHz
MHz
MHz
V
VPP
V
VPP
V
VPP
V
VPP
ps
%
8
Rev. 0.6
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