MUSA16P14-B456C 데이터 시트보기 (PDF) - Music Semiconductors

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MUSA16P14-B456C

Epoch MultiLayer Switch Chipset

Music Semiconductors 

Functional Overview

Epoch MultiLayer Switch Chipset

Buffer Manager (BFM)

The Buffer Manager (BFM) is responsible for storing and

extracting packets from the SDRAM. All packet switching

occurs in the SDRAM. The Packet Data SDRAM stores

the packet data received by the Epoch. The Packet Control

SDRAM stores linked list information as well as data

associated with each packet. Separate SDRAMs are used

for packet data and BFM control information. If a packet

is larger than the size of a buffer, then the BFM is

responsible for chaining together buffers to hold an entire

packet.

The BFM also tracks the number of queues that point to

each packet. This number decrements after packet

transmission. When this number reaches zero, the buffers

return to the free buffer pool.

L3/L4 Database

The L3/L4 Database RCP consists of up to four cascaded

RCPs from the MUSIC MUAC Routing CoProcessor

family. These RCPs provide the ability to perform 32-bit

longest match address lookup or 64-bit exact address

lookup. The RCPs contain the IP, IPX and IP Multicast

routing tables, along with matched (see CRI section),

authenticated flow information. See MUSIC Application

Note AN-N25 for more detailed information on Layer 3

address lookup. See MUSIC Application Note AN-N27

for more detailed information on Layer 4 flow recognition.

RCP/RAM Interface (CRI)

The RCP/RAM Interface (CRI) interface contains the state

machines for driving the RCP and associated data RAM as

well as the logic to arbitrate among the sources of RCP

operations (PEN and PIM).

Database SRAM

The external L3/L4 Database SRAM contains the

Differentiated Services data associated with each word

contained in the L3/L4 Database RCP as well as default

queuing information based on TCP/UDP port number for

unrecognized flows and the Differentiated Services BAC

mode Table.

Parse Engine (PEN)

The Parse Engine (PEN) comprises the L3 data

manipulation, L3 Lookup and L4 Lookup sections. The L3

Data Parse Engine makes the appropriate changes to the

header of each IP or IPX packet that passes through the

Epoch, such as decrementing the TTL field and

recomputing the header checksum on IP or the Transport

Control field on IPX. If the packet is not an IP or IPX

packet, the header is unchanged. The PEN verifies various

fields of the IPv4 or IPX header.

The L3 Engine in the PEN is responsible for extracting the

IPv4, IP Multicast, or IPX address from the packet and

using the RCP (via the CRI) to determine the output

port(s) to which the packet is to be sent. The RCP returns

the index of a matching entry and this index selects a

16-bit output port bitmap from a separate SRAM (via the

CRI). If the packet is directly queued because it is not an

IP or IPX packet, information passed to the Epoch on the

control bus determines the port(s) for the packet.

The L4 Parse Engine in the PEN recognizes distinct packet

flows travelling through the network. Traffic may be

classified using the proposed IETF Differentiated

Services. Filtering is also supported on a per flow basis.

Traffic is classified in one of two modes:

• BAC (Behavior Aggregate Classification) Mode: The

DS field is used to address a RAM that returns a

Queue number for the destination port. The Mapping

Table is processor maintained.

• Microflow Mode: The parse engine extracts the IP

and L4 header including TCP or UDP port number,

source and destination IP address fields and incoming

L2 interface number. Packets are then prioritized to

one of eight queues on the destination port from the

default flow table or from the matched flow table if a

match is found.

Packet Manager (PKM)

The Packet Manager (PKM) inserts and extracts packet

pointers from queues. During packet reception, the PKM

receives a queue number and packet pointer from the

MCM, and adds the packet pointer at the tail of the

specified queue. During packet transmission, the PKM

receives a queue number from the Queue Scheduler

Module (QSM), and it extracts the packet pointer at the

head of the specified queue and passes it to the BFM.

The internal queue pointer SRAM contains the

information that associates packets with queues. The QSM

determines the service order for output port queues. The

QSM returns the queue number (if any) for the next

transmission.

PIM and STM Modules

The Processor Interface Module (PIM) interfaces an

external processor to the Epoch. The processor has access

to various blocks of RAM and RCP, as well as a number of

registers for controlling and monitoring the Epoch.

The Statistics Module (STM) accumulates counts of

dropped packets.

Rev. 2.7 Draft

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