MUSA16P14-B456C 데이터 시트보기 (PDF) - Music Semiconductors

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MUSA16P14-B456C

Epoch MultiLayer Switch Chipset

Music Semiconductors 

Epoch MultiLayer Switch Chipset

Operational Overview

OPERATIONAL OVERVIEW

The MUSIC Epoch MultiLayer Switch Chip for a Layer

3/4 switch performs all of the functions necessary to route

IPv4, IPX and IP Multicast packets at wire-speed; to

recognize and categorize traffic flows, optionally using

IETF Differentiated Services (DS); and to queue each flow

independently in an associated SDRAM. Upon

transmission, DS information may be remarked. The

Epoch handles up to 16 ports; one port is required for the

processor to allow it to act as a packet source or

destination.

The Epoch chip fits into a system as shown in Figure 1.

The Epoch chip itself is the heart of the system and forms

the basis of a Layer 3/4 switch with up to 16 ports, one of

which is used for the processor to send and receive

packets. Each port has eight queues and a queue scheduler

determines queue service order for each output port. Layer

3 and Layer 4 information are stored in a Routing

CoProcessor (RCP) database. The RCP provides the

packet header processing performance necessary to do true

wire-speed packet-by-packet routing and real-time flow

recognition. The Epoch has a multicast switch fabric that

also can be used for Layer 2 switches and xDSL

multiplexers.

Various SRAM and SDRAM devices are required to store

packet data and internal Epoch control information.

A processor provides non-real-time initialization and

housekeeping functions. A processor also is used to handle

packets destined to the switch and packets not supported

by the Epoch. One processor may be used to handle both

of these functions or separate processors may be used.

The Arbiter controls access to the bidirectional data bus

among the Layer 2 ports, including the processor interface

to the data bus. These components are detailed later.

Layer 2

Interface(s)

Arbiter Bus

Arbiter

Data Bus

Control Bus

Processor

Interface

Processor Bus

MUSIC Semiconductors

EPOCH MultiLayer Switch

MUAC Bus

MUSIC

Semiconductors

MUAC Routing

CoProcessor

4K-32K x 64

SRAM Bus

L3/L4

Database

SRAM

128K x 16

Processor or

Processors

Packet Data

SDRAM

1M x 16 (2x)

Packet

Control

SDRAM

1M x 16

Packet

Pointer

SRAM

64K x 32

Note: Solid boxes denote MUSIC standard products; dashed boxes denote either standard products; dashed boxes denote standard products from other

manufacturers or customer ASICs/FPGAs/PLDs.

Figure 1: EPOCH MultiLayer Switch in a System

2

Rev. 2.7 Draft

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