MICRF002BN 데이터 시트보기 (PDF) - Micrel

부품명

상세내역

제조사

MICRF002BN

QwikRadio™ Low Power UHF Receiver

Micrel 

MICRF002

QwikRadio tm

Pin Description (Pin numbers for the 8-pin version are identified in parentheses)

Micrel

Pin Number

1

2/3

(1)

4

(2)

5

6

(3)

7

(4)

8

9

10

(5)

11

(6)

12

13

(7)

14

15

(8)

16

Pin Name

SEL0

VSSRF

VSS

ANT

VDDRF

VDDBB

VDD

CTH

N/C

VSSBB

DO

SHUT

WAKEB

CAGC

SEL1

REFOSC

SWEN

Pin Function

This pin, in conjunction with SEL1, programs the desired Demodulator Filter Bandwidth. This pin is

internally pulled-up to VDD. See Table 1.

This pin is the ground return for the RF section of the IC. The bypass capacitor connected from VDDRF to

VSSRF should have the shortest possible lead length. For best performance, connect VSSRF to VSSBB

at the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).

This pin is the ground return for the IC. The bypass capacitor connected from VDD to VSS should have

the shortest possible lead length.

This is the receive RF input, internally ac-coupled. Connect this pin to the receive antenna. Input

impedance is high (FET gate) with approximately 2pF of shunt (parasitic) capacitance. For applications

located in high ambient noise environments, a fixed value band-pass network may be connected between

the ANT pin and VSSRF to provide additional receive selectivity and input overload protection. (See

“Application Note TBD”.)

This pin is the positive supply input for the RF section of the IC. VDDBB and VDDRF should be connected

directly at the IC pins. Connect a low ESL, low ESR decoupling capacitor from this pin to VSSRF, as short

as possible.

This pin is the positive supply input for the baseband section of the IC. VDDBB and VDDRF should be

connected directly at the IC pins.

This pin is the positive supply input for the IC. Connect a low ESL, low ESR decoupling capacitor from this

pin to VSSRF, as short as possible.

This capacitor extracts the (DC) average value from the demodulated waveform, which becomes the

reference for the internal data slicing comparator. Treat this as a low-pass RC filter with source impedance

of 118kΩ (for REFOSC frequency ft = 4.90MHz, see Note 5). A standard ± 20% X7R ceramic capacitor is

generally sufficient.

Unused Pin

This is the ground return for the baseband section of the IC. The bypass and output capacitors connected

to VSSBB should have the shortest possible lead lengths. For best performance, connect VSSRF to

VSSBB at the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).

The output data signal. CMOS level compatible.

A logic input for Shutdown Mode control. Pull this pin low to place the IC into operation. This pin in

internally pulled-up to VDD.

An output signal, active low when the IC detects an incoming RF signal, determined by monitoring for data

preamble. CMOS level compatible.

Integrating capacitor for on-chip AGC (Automatic Gain Control). The Decay/Attack time-constant (TC) ratio

is nominally set as 10:1. Use of 0.47uF or greater is strongly recommended for best range performance.

Use low-leakage type capacitors for duty-cycle operation (Dip Tantalum, Ceramic, Polyester). (See

“Application Note TBD.)

This pin, in conjunction with SEL0, programs the desired Demodulator Filter Bandwidth. This pin in

internally pulled-up to VDD. See Table 1.

This is the timing reference for on-chip tuning and alignment. Connect either a ceramic resonator or crystal

(mode dependent) between this pin and VSSBB, or drive the input with an AC coupled 0.5Vpp input clock.

Use ceramic resonators without integral capacitors. Note that if operating in FIXED mode, a crystal must

be used; however in SWP mode, one may use either a crystal or ceramic resonator. See “Application Note

TBD” for details on frequency selection and accuracy.

This logic pin controls the operating mode of the MICRF002. When SWEN = HIGH, the MICRF002 is in

SWP mode. When SWEN = LOW, the device operates as a conventional single-conversion

superheterodyne receiver. (See “Application Note TBD” for details.) This pin is internally pulled-up to VDD.

SEL0

1

0

1

0

SEL1

1

1

0

0

SWP Mode

5000

2500

1250

625

Demodulator Bandwidth (Hz)

FIXED Mode

10000

5000

2500

1250

Table 1

Nominal Demodulator (Baseband) Filter Bandwidth

vs. SEL0, SEL1 and Mode

July 1999

3

MICRF002

Share Link: