HMP9701A 데이터 시트보기 (PDF) - Intersil

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HMP9701A

AC’97 Audio Codec

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HMP9701A

TABLE 15. RECORD SELECT LEFT CHANNEL

SL2:0

RIGHT RECORD SOURCE

0

MIC

1

CD_L

2

VIDEO_L

3

AUX_L

4

LINE_IN_L

5

Stereo Mix Right

6

Mono Mix

7

PHONE

Default: 000 (MIC in)

TABLE 18. POWERDOWN CONTROL

BIT

FUNCTION

PR0 Input Mux and ADC’s (1 = PWR Down, 0 = PWR Up)

PR1 DACs (1 = PWR Down, 0 = PWR Up)

PR2 Analog Mixer Powerdown with VREF Left On

(1 = PWR Down, 0 = PWR Up)

PR3 Analog Mixer Powerdown with VREF Turned Off

(1 = PWR Down, 0 = PWR Up)

PR4 Digital Interface (AC Link) powerdown (BCLK off)

(1 = PWR Down, 0 = PWR Up)

PR5 Internal Clock Disable (1 = CLK Off, 0 = CLK On)

Default: na

Record Gain Registers (Index 1Ch and 1Eh)

These registers control the record gain for both the MIC

input and the selected stereo inputs (see Record Select

Register). The gain is programmed in steps of 1.5dB and

ranges from 0dB to +22.5dB. The MSB of the register is the

mute bit. When this bit is set to 1 the level for that channel(s)

is set at -∞dB.

The lower byte of this register is used to monitor the status of

individual sections with in the HMP9701A. The status bits,

as summarized in Table 19, indicate whether a subsection is

in it’s normal operational state (Ready). Note: the status bits

are read only, and writes to this register will have no effect on

the state of these bits.

TABLE 19. POWERDOWN STATUS

TABLE 16. RECORD GAIN SETTINGS

MUTE

PV3:0

FUNCTION

0

0 1111

+22.5dB Gain

0

0 0000

0dB Gain

1

x xxxx

-∞dB Gain

Default: 8000h (0dB Gain with Mute on)

General Purpose Register (Index 20h)

This register is used to control several miscellaneous func-

tions within the HMP9701A. These include the selection of

Mic input source, the selection of MONO_OUT source, and

activation of ADC/DAC loopback mode. When loopback

mode is enabled, the ADC output is looped back to the DAC

input bypassing the AC-link, thus allowing for full system per-

formance measurements.

BIT

FUNCTION

REF

ANL

VREFs at Nominal Level

(1 = VREF Ready, 0 = VREF Down)

Analog Mixer Powerdown

(1 = Mixer Up, 0 = Mixer Down)

DAC DAC Ready for Audio Samples

(1 = Ready, 0 = Not Ready)

ADC ADC Section Ready to Record

(1 = Ready, 0 = Not Ready)

Default: na

When the AC-link “Codec Ready” indicator bit (SDATA_IN

slot 0, bit 15) is a 1, it indicates that the AC-link and AC‘97

control and status registers are in a fully operational state. It

is the responsibility of the digital controller to further probe

the Powerdown Control/Status Register to determine exactly

which subsections, if any, are ready.

TABLE 17. GENERAL PURPOSE CONTROL

BIT

FUNCTION

MIX

Mono Output Select (0 = Mix, 1 = MIC)

MS

Mic Select (1 = Mic2, 0 = Mic1)

LPBK

ADC/DAC Loopback Mode

Default: 0000h

Powerdown Control/Status Register (Index 26h)

This register is used to program the HMP9701A’s power-

down states and monitor subsystem status. The upper bits

of this register are used to power up/down individual sec-

tions within the codec as summarized in Table 18.

Reserved Registers (Index 28h - 7ah)

These are reserved. Do not write to these registers.

Vendor ID Registers (Index 7Ch - 7Eh)

This register contains the Harris Semiconductor vendor ID.

The ID method is a Microsoft’s Plug and Play Vendor ID

code with F7:0 the first character of that ID, S7:0 the second

character and T7:0 the third character. These three charac-

ters are ASCII encoded, and they will read back as ‘HRS’.

The REV7:0 field is for the Revision number.

9

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