UT62L5128LC-55LE 데이터 시트보기 (PDF) - Utron Technology Inc
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UT62L5128LC-55LE Datasheet PDF : 12 Pages
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Rev. 1.1
UTRON
CAPACITANCE (TA=25℃, f=1.0MHz)
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN
-
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
MAX
6
8
UNIT
pF
pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
CL = 30pF, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA =0℃ to 70℃ / -20℃ to 80℃(E))
(1) READ CYCLE
PARAMETER
SYMBOL
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
UT62L5128-55*
MIN. MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
5
-
UT62L5128-70
MIN. MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
5
-
UT62L5128-100
MIN. MAX.
100
-
-
100
-
100
-
50
10
-
5
-
-
30
-
35
5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
UT62L5128-55*
MIN. MAX.
55
-
50
-
50
-
0
-
45
-
0
-
25
-
0
-
5
-
-
30
UT62L5128-70
MIN. MAX.
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
30
*These parameters are guaranteed by device characterization, but not production tested.
*55ns for Vcc=3.0V~3.6V
UT62L5128-100
MIN. MAX.
100
-
80
-
80
-
0
-
70
-
0
-
40
-
0
-
5
-
-
40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
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