MX29F800B 데이터 시트보기 (PDF) - Macronix International

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MX29F800B

8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY

Macronix International 

MX29F800T/B

Q5

Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-

ceeded the specified limits(internal pulse count). Un-

der these conditions Q5 will produce a "1". This time-

out condition indicates that the program or erase cycle

was not successfully completed. Data Polling and Toggle

Bit are the only operating functions of the device under

this condition.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence.

This allows the system to continue to use the other ac-

tive sectors in the device.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously

protected sector to change data in-system. The Tempo-

rary Sector Unprotect mode is activated by setting the

RESET pin to VID(11.5V-12.5V). During this mode, for-

merly protected sectors can be programmed or erased

as un-protected sector. Once VID is remove from the

RESET pin,all the previously protected sectors are pro-

tected again.

Q3

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

and Toggle Bit are valid after the initial sector erase com-

mand sequence.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector maynot be re-

used, (other sectors are still functional and can be re-

used).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops tog-

gling. Once the Device has exceeded timing limits, the

Q5 bit will indicate a "1". Please note that this is not a

device failure condition since the device was incorrectly

used.

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept addi-

tional sector erase commands. To insure the command

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been ac-

cepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will

not initiate a write cycle.

DATA PROTECTION

The MX29F800T/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during

power transition. During power up the device automati-

cally resets the state machine in the Read mode. In

addition, with its control register architecture, alteration

of the memory contents only occurs after successful

completion of specific command sequences. The de-

vice also incorporates several features to prevent inad-

vertent write cycles resulting from VCC power-up and

power-down transition or system noise.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE

= VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND.

P/N:PM0578

REV. 1.7, JUL. 24, 2001

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